文件名称:CPU
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用VHDL设计的cpu 用微指令方法设计 通过rom查表的方式进行设计-Cpu design with VHDL designed by microinstructions way through the design of look-up table rom
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下载文件列表
CPU\ALU.bsf
...\ALU.vhd
...\ALU.vhd.bak
...\CAR.bsf
...\CAR.vhd
...\CAR.vhd.bak
...\CBR.bsf
...\CBR.vhd
...\CBR.vhd.bak
...\clkprocess.bsf
...\clkprocess.vhd
...\clkprocess.vhd.bak
...\CPU.asm.rpt
...\CPU.done
...\CPU.fit.rpt
...\CPU.fit.smsg
...\CPU.fit.summary
...\CPU.flow.rpt
...\CPU.map.rpt
...\CPU.map.summary
...\CPU.pin
...\CPU.pof
...\CPU.qpf
...\CPU.qsf
...\CPU.qws
...\CPU.sim.rpt
...\CPU.sof
...\CPU.tan.rpt
...\CPU.tan.summary
...\CPU.vht
...\cputest.vwf
...\db\altsyncram_g791.tdf
...\..\altsyncram_j081.tdf
...\..\altsyncram_lg81.tdf
...\..\altsyncram_oga1.tdf
...\..\altsyncram_r3p1.tdf
...\..\altsyncram_r6r1.tdf
...\..\CPU.asm.qmsg
...\..\CPU.asm_labs.ddb
...\..\CPU.cbx.xml
...\..\CPU.cmp.cdb
...\..\CPU.cmp.hdb
...\..\CPU.cmp.logdb
...\..\CPU.cmp.rdb
...\..\CPU.cmp.tdb
...\..\CPU.cmp0.ddb
...\..\CPU.cmp2.ddb
...\..\CPU.dbp
...\..\CPU.db_info
...\..\CPU.eco.cdb
...\..\CPU.eds_overflow
...\..\CPU.fit.qmsg
...\..\CPU.fnsim.cdb
...\..\CPU.fnsim.hdb
...\..\CPU.fnsim.qmsg
...\..\CPU.hier_info
...\..\CPU.hif
...\..\CPU.map.cdb
...\..\CPU.map.ecobp
...\..\CPU.map.hdb
...\..\CPU.map.logdb
...\..\CPU.map.qmsg
...\..\CPU.map_bb.logdb
...\..\CPU.pre_map.cdb
...\..\CPU.pre_map.hdb
...\..\CPU.psp
...\..\CPU.pss
...\..\CPU.rtlv.hdb
...\..\CPU.rtlv_sg.cdb
...\..\CPU.rtlv_sg_swap.cdb
...\..\CPU.sgdiff.cdb
...\..\CPU.sgdiff.hdb
...\..\CPU.signalprobe.cdb
...\..\CPU.sim.cvwf
...\..\CPU.sim.hdb
...\..\CPU.sim.qmsg
...\..\CPU.sim.rdb
...\..\CPU.simfam
...\..\CPU.sim_ori.vwf
...\..\CPU.sld_design_entry.sci
...\..\CPU.sld_design_entry_dsc.sci
...\..\CPU.syn_hier_info
...\..\CPU.tan.qmsg
...\..\CPU.tis_db_list.ddb
...\..\mult_9v01.tdf
...\..\prev_cmp_CPU.asm.qmsg
...\..\prev_cmp_CPU.fit.qmsg
...\..\prev_cmp_CPU.map.qmsg
...\..\prev_cmp_CPU.qmsg
...\..\prev_cmp_CPU.sim.qmsg
...\..\prev_cmp_CPU.tan.qmsg
...\..\wed.wsf
...\IR.bsf
...\IR.vhd
...\IR.vhd.bak
...\IRdecode.hex
...\lpm_ram_dq0.bsf
...\lpm_ram_dq0.cmp
...\lpm_ram_dq0.vhd
...\lpm_ram_dq0_wave0.jpg
...\ALU.vhd
...\ALU.vhd.bak
...\CAR.bsf
...\CAR.vhd
...\CAR.vhd.bak
...\CBR.bsf
...\CBR.vhd
...\CBR.vhd.bak
...\clkprocess.bsf
...\clkprocess.vhd
...\clkprocess.vhd.bak
...\CPU.asm.rpt
...\CPU.done
...\CPU.fit.rpt
...\CPU.fit.smsg
...\CPU.fit.summary
...\CPU.flow.rpt
...\CPU.map.rpt
...\CPU.map.summary
...\CPU.pin
...\CPU.pof
...\CPU.qpf
...\CPU.qsf
...\CPU.qws
...\CPU.sim.rpt
...\CPU.sof
...\CPU.tan.rpt
...\CPU.tan.summary
...\CPU.vht
...\cputest.vwf
...\db\altsyncram_g791.tdf
...\..\altsyncram_j081.tdf
...\..\altsyncram_lg81.tdf
...\..\altsyncram_oga1.tdf
...\..\altsyncram_r3p1.tdf
...\..\altsyncram_r6r1.tdf
...\..\CPU.asm.qmsg
...\..\CPU.asm_labs.ddb
...\..\CPU.cbx.xml
...\..\CPU.cmp.cdb
...\..\CPU.cmp.hdb
...\..\CPU.cmp.logdb
...\..\CPU.cmp.rdb
...\..\CPU.cmp.tdb
...\..\CPU.cmp0.ddb
...\..\CPU.cmp2.ddb
...\..\CPU.dbp
...\..\CPU.db_info
...\..\CPU.eco.cdb
...\..\CPU.eds_overflow
...\..\CPU.fit.qmsg
...\..\CPU.fnsim.cdb
...\..\CPU.fnsim.hdb
...\..\CPU.fnsim.qmsg
...\..\CPU.hier_info
...\..\CPU.hif
...\..\CPU.map.cdb
...\..\CPU.map.ecobp
...\..\CPU.map.hdb
...\..\CPU.map.logdb
...\..\CPU.map.qmsg
...\..\CPU.map_bb.logdb
...\..\CPU.pre_map.cdb
...\..\CPU.pre_map.hdb
...\..\CPU.psp
...\..\CPU.pss
...\..\CPU.rtlv.hdb
...\..\CPU.rtlv_sg.cdb
...\..\CPU.rtlv_sg_swap.cdb
...\..\CPU.sgdiff.cdb
...\..\CPU.sgdiff.hdb
...\..\CPU.signalprobe.cdb
...\..\CPU.sim.cvwf
...\..\CPU.sim.hdb
...\..\CPU.sim.qmsg
...\..\CPU.sim.rdb
...\..\CPU.simfam
...\..\CPU.sim_ori.vwf
...\..\CPU.sld_design_entry.sci
...\..\CPU.sld_design_entry_dsc.sci
...\..\CPU.syn_hier_info
...\..\CPU.tan.qmsg
...\..\CPU.tis_db_list.ddb
...\..\mult_9v01.tdf
...\..\prev_cmp_CPU.asm.qmsg
...\..\prev_cmp_CPU.fit.qmsg
...\..\prev_cmp_CPU.map.qmsg
...\..\prev_cmp_CPU.qmsg
...\..\prev_cmp_CPU.sim.qmsg
...\..\prev_cmp_CPU.tan.qmsg
...\..\wed.wsf
...\IR.bsf
...\IR.vhd
...\IR.vhd.bak
...\IRdecode.hex
...\lpm_ram_dq0.bsf
...\lpm_ram_dq0.cmp
...\lpm_ram_dq0.vhd
...\lpm_ram_dq0_wave0.jpg