文件名称:FPGA-CPLD_DesignTool(8-9-10)
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压缩包 : 83390084fpga-cpld_designtool(8-9-10).rar 列表 Example-9-1\synplify_pro_prj\Synplify_Pro\black_box.v Example-9-1\synplify_pro_prj\Synplify_Pro\cnt60.vf Example-9-1\synplify_pro_prj\Synplify_Pro\dcm1.v Example-9-1\synplify_pro_prj\Synplify_Pro\decode.v Example-9-1\synplify_pro_prj\Synplify_Pro\hex2led.v Example-9-1\synplify_pro_prj\Synplify_Pro\outs3.vf Example-9-1\synplify_pro_prj\Synplify_Pro\STMACH_V.v Example-9-1\synplify_pro_prj\Synplify_Pro\stopwatch.vf Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\STMACH_V.plg Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\STMACH_V.srd Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.edf Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.fse Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.ncf Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.plg Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.srd Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.srm Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.srr Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.srs Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.tlg Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.edf Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.fse Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.ncf Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.plg Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.srd Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.srm Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.srr Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.srs Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.tlg Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1 Example-9-1\synplify_pro_prj\Synplify_Pro\Syn_Pro_stopwatch.prd Example-9-1\synplify_pro_prj\Synplify_Pro\Syn_Pro_stopwatch.prj Example-9-1\synplify_pro_prj\Synplify_Pro\Syn_Pro_stopwatch.sdc Example-9-1\synplify_pro_prj\Synplify_Pro\tenths.v Example-9-1\synplify_pro_prj\Synplify_Pro\virtex2p.v Example-9-1\synplify_pro_prj\Synplify_Pro Example-9-1\synplify_pro_prj\综合所需的源代码\black_box.v Example-9-1\synplify_pro_prj\综合所需的源代码\cnt60.vf Example-9-1\synplify_pro_prj\综合所需的源代码\dcm1.v Example-9-1\synplify_pro_prj\综合所需的源代码\decode.v Example-9-1\synplify_pro_prj\综合所需的源代码\hex2led.v Example-9-1\synplify_pro_prj\综合所需的源代码\outs3.vf Example-9-1\synplify_pro_prj\综合所需的源代码\STMACH_V.v Example-9-1\synplify_pro_prj\综合所需的源代码\stopwatch.vf Example-9-1\synplify_pro_prj\综合所需的源代码\tenths.v Example-9-1\synplify_pro_prj\综合所需的源代码\virtex2p.v Example-9-1\synplify_pro_prj\综合所需的源代码 Example-9-1\synplify_pro_prj Example-9-1\watch_sc_v5\.untf Example-9-1\watch_sc_v5\AndNor2.sch Example-9-1\watch_sc_v5\automake.log Example-9-1\watch_sc_v5\bitgen.ut Example-9-1\watch_sc_v5\cnt60.cmd_log Example-9-1\watch_sc_v5\cnt60.jhd Example-9-1\watch_sc_v5\cnt60.sch Example-9-1\watch_sc_v5\cnt60.sym Example-9-1\watch_sc_v5\cnt60.vhf Example-9-1\watch_sc_v5\core.tpl Example-9-1\watch_sc_v5\coregen.log Example-9-1\watch_sc_v5\DCM1.jhd Example-9-1\watch_sc_v5\dcm1.sym Example-9-1\watch_sc_v5\DCM1.vhd Example-9-1\watch_sc_v5\DCM1.xaw Example-9-1\watch_sc_v5\DCM1_arwz.ucf Example-9-1\watch_sc_v5\decode.jhd Example-9-1\watch_sc_v5\decode.spl Example-9-1\watch_sc_v5\decode.sym Example-9-1\watch_sc_v5\decode.vhd Example-9-1\watch_sc_v5\decode.vhi Example-9-1\watch_sc_v5\hex2led.jhd Example-9-1\watch_sc_v5\hex2led.spl Example-9-1\watch_sc_v5\hex2led.sym Example-9-1\watch_sc_v5\hex2led.vhd Example-9-1\watch_sc_v5\hex2led.vhi Example-9-1\watch_sc_v5\outs3.cmd_log Example-9-1\watch_sc_v5\outs3.jhd Example-9-1\watch_sc_v5\outs3.sch Example-9-1\watch_sc_v5\outs3.sym Example-9-1\watch_sc_v5\outs3.vhf Example-9-1\watch_sc_v5\readme.txt Example-9-1\watch_sc_v5\stmach_v.dia Example-9-1\watch_sc_v5\STMACH_V.jhd Example-9-1\watch_sc_v5\stmach_v.spl Example-9-1\watch_sc_v5\stmach_v.sym Example-9-1\watch_sc_v5\STMACH_V.vhd Example-9-1\watch_sc_v5\stmach_v.vhi Example-9-1\watch_sc_v5\stopwatch.ana Example-9-1\watch_sc_v5\stopwatch.bgn Example-9-1\watch_sc_v5\stopwatch.bit Example-9-1\watch_sc_v5\stopwatch.bld Example-9-1\watch_sc_v5\stopwatch.cmd_log Example-9-1\watch_sc_v5\stopwatch.dly Example-9-1\watch_sc_v5\stopwatch.drc Example-9-1\watch_sc_v5\stopwatch.jhd Example-9-1\watch_sc_v5\stopwatch.mrp Example-9-1\watch_sc_v5\stopwatch.nc1 Example-9-1\watch_sc_v5\stopwatch.ncd Example-9-1\watch_sc_v5\stopwatch.ngc Example-9-1\watch_sc_v5\stopwatch.ngd Example-9-1\watch_sc_v5\stopwatch.ngm Example-9-1\watch_sc_v5\stopwatch.ngr Example-9-1\watch_sc_v5\stopwatch.pad Example-9-1\watch_sc_v5\stopwatch.par Example-9-1\watch_sc_v5\stopwatch.pcf Example-9-1\watch_sc_v5\stopwatch.prj Example-9-1\watch_sc_v5\stopwatch.sch Example-9-1\watch_sc_v5\stopwatch.schbak Example-9-1\watch_sc_v5\stopwatch.schcmd Example-9-1\watch_sc_v5\stopwatch.sprj Example-9-1\watch_sc_v5\stopwatch.stx Example-9-1\watch_sc_v5\stopwatch.sym Example-9-1\watch_sc_v5\stopwatch.syr Example-9-1\watch_sc_v5\stopwatch.twr Example-9-1\watch_sc_v5\stopwatch.twx Example-9-1\watch_sc_v5\stopwatch.ut Example-9-1\watch_sc_v5\stopwatch.vhdsim_xlate Example-9-1\watch_sc_v5\stopwatch.vhf Example-9-1\watch_sc_v5\stopwatch.xpi Example-9-1\watch_sc_v5\stopwatch_map.ncd Example-9-1\watch_sc_v5\stopwatch_map.ngm Example-9-1\watch_sc_v5\stopwatch_ngdbuild.nav Example-9-1\watch_sc_v5\stopwatch_tb.jhd Example-9-1\watch_sc_v5\stopwatch_tb.vhd Example-9-1\watch_sc_v5\stopwatch_translate.vhd Example-9-1\watch_sc_v5\tenths.asy Example-9-1\watch_sc_v5\tenths.coregen_log Example-9-1\watch_sc_v5\tenths.edn Example-9-1\watch_sc_v5\tenths.jhd Example-9-1\watch_sc_v5\tenths.ngo Example-9-1\watch_sc_v5\tenths.sym Example-9-1\watch_sc_v5\tenths.v Example-9-1\watch_sc_v5\tenths.veo Example-9-1\watch_sc_v5\tenths.vhd Example-9-1\watch_sc_v5\tenths.vho Example-9-1\watch_sc_v5\tenths.xco Example-9-1\watch_sc_v5\tenths.xcp Example-9-1\watch_sc_v5\tenths_flist.txt Example-9-1\watch_sc_v5\userlang.tpl Example-9-1\watch_sc_v5\watch.sch Example-9-1\watch_sc_v5\wtut_sc.npl Example-9-1\watch_sc_v5\wtut_sc.ptf Example-9-1\watch_sc_v5\xst\work\hdpdeps.ref Example-9-1\watch_sc_v5\xst\work\sub00\vhpl00.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl01.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl02.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl03.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl04.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl05.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl06.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl07.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl08.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl09.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl10.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl11.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl12.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl13.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl14.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl15.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl16.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl17.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl18.vho Example-9-1\watch_sc_v5\xst\work\sub00\vhpl19.vho Example-9-1\watch_sc_v5\xst\work\sub00 Example-9-1\watch_sc_v5\xst\work\vhdllib.ref Example-9-1\watch_sc_v5\xst\work Example-9-1\watch_sc_v5\xst Example-9-1\watch_sc_v5\_ngo\netlist.lst Example-9-1\watch_sc_v5\_ngo\tenths.ngo Example-9-1\watch_sc_v5\_ngo Example-9-1\watch_sc_v5\_tmp_\coretmpdir Example-9-1\watch_sc_v5\_tmp_ Example-9-1\watch_sc_v5\__projnav\bitgen.rsp Example-9-1\watch_sc_v5\__projnav\ednTOngd_tcl.rsp Example-9-1\watch_sc_v5\__projnav\map.log Example-9-1\watch_sc_v5\__projnav\mapFloorPlanner.rsp Example-9-1\watch_sc_v5\__projnav\nc1TOncd_tcl.rsp Example-9-1\watch_sc_v5\__projnav\ngd2vhdl.log Example-9-1\watch_sc_v5\__projnav\p007m000.kis Example-9-1\watch_sc_v5\__projnav\p00p5000.kis Example-9-1\watch_sc_v5\__projnav\p00pz000.kis Example-9-1\watch_sc_v5\__projnav\par.log Example-9-1\watch_sc_v5\__projnav\posttrc.log Example-9-1\watch_sc_v5\__projnav\runXst_tcl.rsp Example-9-1\watch_sc_v5\__projnav\stopwatch.err Example-9-1\watch_sc_v5\__projnav\stopwatch.xst Example-9-1\watch_sc_v5\__projnav\stopwatch._prj Example-9-1\watch_sc_v5\__projnav\stopwatch._sprj Example-9-1\watch_sc_v5\__projnav\stopwatch_ncdTOut_tcl.rsp Example-9-1\watch_sc_v5\__projnav\tb.rsp Example-9-1\watch_sc_v5\__projnav\wtut_sc.gfl Example-9-1\watch_sc_v5\__projnav\wtut_sc_flowplus.gfl Example-9-1\watch_sc_v5\__projnav Example-9-1\watch_sc_v5\__projnav.log Example-9-1\watch_sc_v5 Example-9-1\watch_sc_v6\.untf Example-9-1\watch_sc_v6\AndNor2.sch Example-9-1\watch_sc_v6\automake.log Example-9-1\watch_sc_v6\bitgen.ut Example-9-1\watch_sc_v6\cnt60.sch Example-9-1\watch_sc_v6\cnt60.sym Example-9-1\watch_sc_v6\cnt60.vf Example-9-1\watch_sc_v6\core.tpl Example-9-1\watch_sc_v6\coregen.log Example-9-1\watch_sc_v6\coregen.prj Example-9-1\watch_sc_v6\DCM1.spl Example-9-1\watch_sc_v6\dcm1.sym Example-9-1\watch_sc_v6\DCM1.tfi Example-9-1\watch_sc_v6\dcm1.v Example-9-1\watch_sc_v6\DCM1.vhd Example-9-1\watch_sc_v6\dcm1.xaw Example-9-1\watch_sc_v6\dcm1_arwz.ucf Example-9-1\watch_sc_v6\DCM1_jhdparse_tcl.rsp Example-9-1\watch_sc_v6\dcm_1.xaw Example-9-1\watch_sc_v6\decode.spl Example-9-1\watch_sc_v6\decode.sym Example-9-1\watch_sc_v6\decode.vhd Example-9-1\watch_sc_v6\hex2led.spl Example-9-1\watch_sc_v6\hex2led.sym Example-9-1\watch_sc_v6\hex2led.vhd Example-9-1\watch_sc_v6\outs3.sch Example-9-1\watch_sc_v6\outs3.sym Example-9-1\watch_sc_v6\outs3.vf Example-9-1\watch_sc_v6\pepExtractor.prj Example-9-1\watch_sc_v6\stmach_v.dia Example-9-1\watch_sc_v6\stmach_v.spl Example-9-1\watch_sc_v6\stmach_v.sym Example-9-1\watch_sc_v6\STMACH_V.vhd Example-9-1\watch_sc_v6\stopwatch.bgn Example-9-1\watch_sc_v6\stopwatch.bit Example-9-1\watch_sc_v6\stopwatch.bld Example-9-1\watch_sc_v6\stopwatch.cmd_log Example-9-1\watch_sc_v6\stopwatch.drc Example-9-1\watch_sc_v6\stopwatch.lso Example-9-1\watch_sc_v6\stopwatch.mrp Example-9-1\watch_sc_v6\stopwatch.nc1 Example-9-1\watch_sc_v6\stopwatch.ncd Example-9-1\watch_sc_v6\stopwatch.ngc Example-9-1\watch_sc_v6\stopwatch.ngd Example-9-1\watch_sc_v6\stopwatch.ngm Example-9-1\watch_sc_v6\stopwatch.ngr Example-9-1\watch_sc_v6\stopwatch.pad Example-9-1\watch_sc_v6\stopwatch.pad_txt Example-9-1\watch_sc_v6\stopwatch.par Example-9-1\watch_sc_v6\stopwatch.pcf Example-9-1\watch_sc_v6\stopwatch.placed_ncd_tracker Example-9-1\watch_sc_v6\stopwatch.prj Example-9-1\watch_sc_v6\stopwatch.routed_ncd_tracker Example-9-1\watch_sc_v6\stopwatch.sch Example-9-1\watch_sc_v6\stopwatch.stx Example-9-1\watch_sc_v6\stopwatch.syr Example-9-1\watch_sc_v6\stopwatch.twr Example-9-1\watch_sc_v6\stopwatch.twx Example-9-1\watch_sc_v6\stopwatch.ut Example-9-1\watch_sc_v6\stopwatch.vf Example-9-1\watch_sc_v6\stopwatch.xpi Example-9-1\watch_sc_v6\stopwatch_last_par.ncd Example-9-1\watch_sc_v6\stopwatch_map.ncd Example-9-1\watch_sc_v6\stopwatch_map.ngm Example-9-1\watch_sc_v6\stopwatch_pad.csv Example-9-1\watch_sc_v6\stopwatch_pad.txt Example-9-1\watch_sc_v6\stopwatch_tb.vhd Example-9-1\watch_sc_v6\stopwatch_translate.vhd Example-9-1\watch_sc_v6\tenths.asy Example-9-1\watch_sc_v6\tenths.edn Example-9-1\watch_sc_v6\tenths.ngo Example-9-1\watch_sc_v6\tenths.sym Example-9-1\watch_sc_v6\tenths.v Example-9-1\watch_sc_v6\tenths.veo Example-9-1\watch_sc_v6\tenths.vhd Example-9-1\watch_sc_v6\tenths.vho Example-9-1\watch_sc_v6\tenths.xco Example-9-1\watch_sc_v6\tenths.xcp Example-9-1\watch_sc_v6\tenths_flist.txt Example-9-1\watch_sc_v6\watch.sch Example-9-1\watch_sc_v6\watch_sc.dhp Example-9-1\watch_sc_v6\watch_sc.npl Example-9-1\watch_sc_v6\xaw2verilog.log Example-9-1\watch_sc_v6\xst\work\hdllib.ref Example-9-1\watch_sc_v6\xst\work\hdpdeps.ref Example-9-1\watch_sc_v6\xst\work\sub00\vhpl00.vho Example-9-1\watch_sc_v6\xst\work\sub00\vhpl01.vho Example-9-1\watch_sc_v6\xst\work\sub00\vhpl02.vho Example-9-1\watch_sc_v6\xst\work\sub00\vhpl03.vho Example-9-1\watch_sc_v6\xst\work\sub00\vhpl04.vho Example-9-1\watch_sc_v6\xst\work\sub00\vhpl05.vho Example-9-1\watch_sc_v6\xst\work\sub00 Example-9-1\watch_sc_v6\xst\work\vlg1D\stopwatch.bin Example-9-1\watch_sc_v6\xst\work\vlg1D Example-9-1\watch_sc_v6\xst\work\vlg1E\tenths.bin Example-9-1\watch_sc_v6\xst\work\vlg1E Example-9-1\watch_sc_v6\xst\work\vlg20\FTCE_MXILINX_cnt60.bin Example-9-1\watch_sc_v6\xst\work\vlg20 Example-9-1\watch_sc_v6\xst\work\vlg37\CB4CE_MXILINX_cnt60.bin Example-9-1\watch_sc_v6\xst\work\vlg37 Example-9-1\watch_sc_v6\xst\work\vlg41\CD4CE_MXILINX_cnt60.bin Example-9-1\watch_sc_v6\xst\work\vlg41 Example-9-1\watch_sc_v6\xst\work\vlg51\dcm1.bin Example-9-1\watch_sc_v6\xst\work\vlg51 Example-9-1\watch_sc_v6\xst\work\vlg66\outs3.bin Example-9-1\watch_sc_v6\xst\work\vlg66 Example-9-1\watch_sc_v6\xst\work\vlg71\DCM1.bin Example-9-1\watch_sc_v6\xst\work\vlg71 Example-9-1\watch_sc_v6\xst\work\vlg7B\cnt60.bin Example-9-1\watch_sc_v6\xst\work\vlg7B Example-9-1\watch_sc_v6\xst\work Example-9-1\watch_sc_v6\xst Example-9-1\watch_sc_v6\_ngo\netlist.lst Example-9-1\watch_sc_v6\_ngo\tenths.ngo Example-9-1\watch_sc_v6\_ngo Example-9-1\watch_sc_v6\__projnav\AndNor2_jhdparse_tcl.rsp Example-9-1\watch_sc_v6\__projnav\bitgen.rsp Example-9-1\watch_sc_v6\__projnav\cnt60_jhdparse_tcl.rsp Example-9-1\watch_sc_v6\__projnav\coregen.rsp Example-9-1\watch_sc_v6\__projnav\DCM1_jhdparse_tcl.rsp Example-9-1\watch_sc_v6\__projnav\dcm_1_jhdparse_tcl.rsp Example-9-1\watch_sc_v6\__projnav\ednTOngd_tcl.rsp Example-9-1\watch_sc_v6\__projnav\map.log Example-9-1\watch_sc_v6\__projnav\nc1TOncd_tcl.rsp Example-9-1\watch_sc_v6\__projnav\outs3_jhdparse_tcl.rsp Example-9-1\watch_sc_v6\__projnav\par.log Example-9-1\watch_sc_v6\__projnav\posttrc.log Example-9-1\watch_sc_v6\__projnav\runXst_tcl.rsp Example-9-1\watch_sc_v6\__projnav\sch2jhd_output.jhd Example-9-1\watch_sc_v6\__projnav\stopwatch.xst Example-9-1\watch_sc_v6\__projnav\stopwatch_jhdparse_tcl.rsp Example-9-1\watch_sc_v6\__projnav\stopwatch_ncdTOut_tcl.rsp Example-9-1\watch_sc_v6\__projnav\v2tfi.err Example-9-1\watch_sc_v6\__projnav\vhd2spl.err Example-9-1\watch_sc_v6\__projnav\watch_jhdparse_tcl.rsp Example-9-1\watch_sc_v6\__projnav\watch_sc.gfl Example-9-1\watch_sc_v6\__projnav\watch_sc_flowplus.gfl Example-9-1\watch_sc_v6\__projnav\xcoTO_regenCore_tenths.rsp Example-9-1\watch_sc_v6\__projnav Example-9-1\watch_sc_v6\__projnav.log Example-9-1\watch_sc_v6 Example-9-1\源文件\AndNor2.sch Example-9-1\源文件\cnt60.sch Example-9-1\源文件\DCM1.vhd Example-9-1\源文件\decode.vhd Example-9-1\源文件\hex2led.vhd Example-9-1\源文件\outs3.sch Example-9-1\源文件\stmach_v.dia Example-9-1\源文件\STMACH_V.vhd Example-9-1\源文件\stopwatch.sch Example-9-1\源文件\stopwatch_tb.vhd Example-9-1\源文件\stopwatch_translate.vhd Example-9-1\源文件\tenths.v Example-9-1\源文件\tenths.vhd Example-9-1\源文件\watch.sch Example-9-1\源文件 Example-9-1\示例说明.doc Example-9-1 Example-10-1\I2C\modelsim\0719.wlf Example-10-1\I2C\modelsim\comp.wlf Example-10-1\I2C\modelsim\format.do Example-10-1\I2C\modelsim\I2C.cr.mti Example-10-1\I2C\modelsim\I2C.mpf Example-10-1\I2C\modelsim\I2C_mapped.cr.mti Example-10-1\I2C\modelsim\I2C_mapped.mpf Example-10-1\I2C\modelsim\rtl_ok.wlf Example-10-1\I2C\modelsim\simprim\dcm_clock_divide_by_2\dcm_clock_divide_by_2_v.asm Example-10-1\I2C\modelsim\simprim\dcm_clock_divide_by_2\dcm_clock_divide_by_2_v.dat Example-10-1\I2C\modelsim\simprim\dcm_clock_divide_by_2\_primary.dat Example-10-1\I2C\modelsim\simprim\dcm_clock_divide_by_2 Example-10-1\I2C\modelsim\simprim\dcm_clock_lost\dcm_clock_lost_v.asm Example-10-1\I2C\modelsim\simprim\dcm_clock_lost\dcm_clock_lost_v.dat Example-10-1\I2C\modelsim\simprim\dcm_clock_lost\_primary.dat Example-10-1\I2C\modelsim\simprim\dcm_clock_lost Example-10-1\I2C\modelsim\simprim\dcm_maximum_period_check\dcm_maximum_period_check_v.asm Example-10-1\I2C\modelsim\simprim\dcm_maximum_period_check\dcm_maximum_period_check_v.dat Example-10-1\I2C\modelsim\simprim\dcm_maximum_period_check\_primary.dat Example-10-1\I2C\modelsim\simprim\dcm_maximum_period_check Example-10-1\I2C\modelsim\simprim\vcomponents\_primary.dat Example-10-1\I2C\modelsim\simprim\vcomponents\_vhdl.asm Example-10-1\I2C\modelsim\simprim\vcomponents Example-10-1\I2C\modelsim\simprim\vpackage\body.asm Example-10-1\I2C\modelsim\simprim\vpackage\body.dat Example-10-1\I2C\modelsim\simprim\vpackage\_primary.dat Example-10-1\I2C\modelsim\simprim\vpackage\_vhdl.asm Example-10-1\I2C\modelsim\simprim\vpackage Example-10-1\I2C\modelsim\simprim\x_and16\x_and16_v.asm Example-10-1\I2C\modelsim\simprim\x_and16\x_and16_v.dat Example-10-1\I2C\modelsim\simprim\x_and16\_primary.dat Example-10-1\I2C\modelsim\simprim\x_and16 Example-10-1\I2C\modelsim\simprim\x_and2\x_and2_v.asm Example-10-1\I2C\modelsim\simprim\x_and2\x_and2_v.dat Example-10-1\I2C\modelsim\simprim\x_and2\_primary.dat Example-10-1\I2C\modelsim\simprim\x_and2 Example-10-1\I2C\modelsim\simprim\x_and3\x_and3_v.asm Example-10-1\I2C\modelsim\simprim\x_and3\x_and3_v.dat Example-10-1\I2C\modelsim\simprim\x_and3\_primary.dat Example-10-1\I2C\modelsim\simprim\x_and3 Example-10-1\I2C\modelsim\simprim\x_and32\x_and32_v.asm Example-10-1\I2C\modelsim\simprim\x_and32\x_and32_v.dat Example-10-1\I2C\modelsim\simprim\x_and32\_primary.dat Example-10-1\I2C\modelsim\simprim\x_and32 Example-10-1\I2C\modelsim\simprim\x_and4\x_and4_v.asm Example-10-1\I2C\modelsim\simprim\x_and4\x_and4_v.dat Example-10-1\I2C\modelsim\simprim\x_and4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_and4 Example-10-1\I2C\modelsim\simprim\x_and5\x_and5_v.asm Example-10-1\I2C\modelsim\simprim\x_and5\x_and5_v.dat Example-10-1\I2C\modelsim\simprim\x_and5\_primary.dat Example-10-1\I2C\modelsim\simprim\x_and5 Example-10-1\I2C\modelsim\simprim\x_and6\x_and6_v.asm Example-10-1\I2C\modelsim\simprim\x_and6\x_and6_v.dat Example-10-1\I2C\modelsim\simprim\x_and6\_primary.dat Example-10-1\I2C\modelsim\simprim\x_and6 Example-10-1\I2C\modelsim\simprim\x_and7\x_and7_v.asm Example-10-1\I2C\modelsim\simprim\x_and7\x_and7_v.dat Example-10-1\I2C\modelsim\simprim\x_and7\_primary.dat Example-10-1\I2C\modelsim\simprim\x_and7 Example-10-1\I2C\modelsim\simprim\x_and8\x_and8_v.asm Example-10-1\I2C\modelsim\simprim\x_and8\x_and8_v.dat Example-10-1\I2C\modelsim\simprim\x_and8\_primary.dat Example-10-1\I2C\modelsim\simprim\x_and8 Example-10-1\I2C\modelsim\simprim\x_and9\x_and9_v.asm Example-10-1\I2C\modelsim\simprim\x_and9\x_and9_v.dat Example-10-1\I2C\modelsim\simprim\x_and9\_primary.dat Example-10-1\I2C\modelsim\simprim\x_and9 Example-10-1\I2C\modelsim\simprim\x_bpad\x_bpad_v.asm Example-10-1\I2C\modelsim\simprim\x_bpad\x_bpad_v.dat Example-10-1\I2C\modelsim\simprim\x_bpad\_primary.dat Example-10-1\I2C\modelsim\simprim\x_bpad Example-10-1\I2C\modelsim\simprim\x_buf\x_buf_v.asm Example-10-1\I2C\modelsim\simprim\x_buf\x_buf_v.dat Example-10-1\I2C\modelsim\simprim\x_buf\_primary.dat Example-10-1\I2C\modelsim\simprim\x_buf Example-10-1\I2C\modelsim\simprim\x_bufgmux\x_bufgmux_v.asm Example-10-1\I2C\modelsim\simprim\x_bufgmux\x_bufgmux_v.dat Example-10-1\I2C\modelsim\simprim\x_bufgmux\_primary.dat Example-10-1\I2C\modelsim\simprim\x_bufgmux Example-10-1\I2C\modelsim\simprim\x_bufgmux_1\x_bufgmux_1_v.asm Example-10-1\I2C\modelsim\simprim\x_bufgmux_1\x_bufgmux_1_v.dat Example-10-1\I2C\modelsim\simprim\x_bufgmux_1\_primary.dat Example-10-1\I2C\modelsim\simprim\x_bufgmux_1 Example-10-1\I2C\modelsim\simprim\x_buf_pp\x_buf_pp_v.asm Example-10-1\I2C\modelsim\simprim\x_buf_pp\x_buf_pp_v.dat Example-10-1\I2C\modelsim\simprim\x_buf_pp\_primary.dat Example-10-1\I2C\modelsim\simprim\x_buf_pp Example-10-1\I2C\modelsim\simprim\x_ckbuf\x_ckbuf_v.asm Example-10-1\I2C\modelsim\simprim\x_ckbuf\x_ckbuf_v.dat Example-10-1\I2C\modelsim\simprim\x_ckbuf\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ckbuf Example-10-1\I2C\modelsim\simprim\x_clkdll\x_clkdll_v.asm Example-10-1\I2C\modelsim\simprim\x_clkdll\x_clkdll_v.dat Example-10-1\I2C\modelsim\simprim\x_clkdll\_primary.dat Example-10-1\I2C\modelsim\simprim\x_clkdll Example-10-1\I2C\modelsim\simprim\x_clkdlle\x_clkdlle_v.asm Example-10-1\I2C\modelsim\simprim\x_clkdlle\x_clkdlle_v.dat Example-10-1\I2C\modelsim\simprim\x_clkdlle\_primary.dat Example-10-1\I2C\modelsim\simprim\x_clkdlle Example-10-1\I2C\modelsim\simprim\x_clkdlle_maximum_period_check\x_clkdlle_maximum_period_check_v.asm Example-10-1\I2C\modelsim\simprim\x_clkdlle_maximum_period_check\x_clkdlle_maximum_period_check_v.dat Example-10-1\I2C\modelsim\simprim\x_clkdlle_maximum_period_check\_primary.dat Example-10-1\I2C\modelsim\simprim\x_clkdlle_maximum_period_check Example-10-1\I2C\modelsim\simprim\x_clkdll_maximum_period_check\x_clkdll_maximum_period_check_v.asm Example-10-1\I2C\modelsim\simprim\x_clkdll_maximum_period_check\x_clkdll_maximum_period_check_v.dat Example-10-1\I2C\modelsim\simprim\x_clkdll_maximum_period_check\_primary.dat Example-10-1\I2C\modelsim\simprim\x_clkdll_maximum_period_check Example-10-1\I2C\modelsim\simprim\x_clk_div\x_clk_div_v.asm Example-10-1\I2C\modelsim\simprim\x_clk_div\x_clk_div_v.dat Example-10-1\I2C\modelsim\simprim\x_clk_div\_primary.dat Example-10-1\I2C\modelsim\simprim\x_clk_div Example-10-1\I2C\modelsim\simprim\x_dcm\x_dcm_v.asm Example-10-1\I2C\modelsim\simprim\x_dcm\x_dcm_v.dat Example-10-1\I2C\modelsim\simprim\x_dcm\_primary.dat Example-10-1\I2C\modelsim\simprim\x_dcm Example-10-1\I2C\modelsim\simprim\x_fdd\x_fdd_v.asm Example-10-1\I2C\modelsim\simprim\x_fdd\x_fdd_v.dat Example-10-1\I2C\modelsim\simprim\x_fdd\_primary.dat Example-10-1\I2C\modelsim\simprim\x_fdd Example-10-1\I2C\modelsim\simprim\x_fddrcpe\x_fddrcpe_v.asm Example-10-1\I2C\modelsim\simprim\x_fddrcpe\x_fddrcpe_v.dat Example-10-1\I2C\modelsim\simprim\x_fddrcpe\_primary.dat Example-10-1\I2C\modelsim\simprim\x_fddrcpe Example-10-1\I2C\modelsim\simprim\x_fddrrse\x_fddrrse_v.asm Example-10-1\I2C\modelsim\simprim\x_fddrrse\x_fddrrse_v.dat Example-10-1\I2C\modelsim\simprim\x_fddrrse\_primary.dat Example-10-1\I2C\modelsim\simprim\x_fddrrse Example-10-1\I2C\modelsim\simprim\x_ff\x_ff_v.asm Example-10-1\I2C\modelsim\simprim\x_ff\x_ff_v.dat Example-10-1\I2C\modelsim\simprim\x_ff\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ff Example-10-1\I2C\modelsim\simprim\x_ibufds\x_ibufds_v.asm Example-10-1\I2C\modelsim\simprim\x_ibufds\x_ibufds_v.dat Example-10-1\I2C\modelsim\simprim\x_ibufds\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ibufds Example-10-1\I2C\modelsim\simprim\x_inv\x_inv_v.asm Example-10-1\I2C\modelsim\simprim\x_inv\x_inv_v.dat Example-10-1\I2C\modelsim\simprim\x_inv\_primary.dat Example-10-1\I2C\modelsim\simprim\x_inv Example-10-1\I2C\modelsim\simprim\x_ipad\x_ipad_v.asm Example-10-1\I2C\modelsim\simprim\x_ipad\x_ipad_v.dat Example-10-1\I2C\modelsim\simprim\x_ipad\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ipad Example-10-1\I2C\modelsim\simprim\x_keeper\x_keeper_v.asm Example-10-1\I2C\modelsim\simprim\x_keeper\x_keeper_v.dat Example-10-1\I2C\modelsim\simprim\x_keeper\_primary.dat Example-10-1\I2C\modelsim\simprim\x_keeper Example-10-1\I2C\modelsim\simprim\x_latch\x_latch_v.asm Example-10-1\I2C\modelsim\simprim\x_latch\x_latch_v.dat Example-10-1\I2C\modelsim\simprim\x_latch\_primary.dat Example-10-1\I2C\modelsim\simprim\x_latch Example-10-1\I2C\modelsim\simprim\x_latche\x_latche_v.asm Example-10-1\I2C\modelsim\simprim\x_latche\x_latche_v.dat Example-10-1\I2C\modelsim\simprim\x_latche\_primary.dat Example-10-1\I2C\modelsim\simprim\x_latche Example-10-1\I2C\modelsim\simprim\x_lut2\x_lut2_v.asm Example-10-1\I2C\modelsim\simprim\x_lut2\x_lut2_v.dat Example-10-1\I2C\modelsim\simprim\x_lut2\_primary.dat Example-10-1\I2C\modelsim\simprim\x_lut2 Example-10-1\I2C\modelsim\simprim\x_lut3\x_lut3_v.asm Example-10-1\I2C\modelsim\simprim\x_lut3\x_lut3_v.dat Example-10-1\I2C\modelsim\simprim\x_lut3\_primary.dat Example-10-1\I2C\modelsim\simprim\x_lut3 Example-10-1\I2C\modelsim\simprim\x_lut4\x_lut4_v.asm Example-10-1\I2C\modelsim\simprim\x_lut4\x_lut4_v.dat Example-10-1\I2C\modelsim\simprim\x_lut4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_lut4 Example-10-1\I2C\modelsim\simprim\x_lut5\x_lut5_v.asm Example-10-1\I2C\modelsim\simprim\x_lut5\x_lut5_v.dat Example-10-1\I2C\modelsim\simprim\x_lut5\_primary.dat Example-10-1\I2C\modelsim\simprim\x_lut5 Example-10-1\I2C\modelsim\simprim\x_lut6\x_lut6_v.asm Example-10-1\I2C\modelsim\simprim\x_lut6\x_lut6_v.dat Example-10-1\I2C\modelsim\simprim\x_lut6\_primary.dat Example-10-1\I2C\modelsim\simprim\x_lut6 Example-10-1\I2C\modelsim\simprim\x_lut7\x_lut7_v.asm Example-10-1\I2C\modelsim\simprim\x_lut7\x_lut7_v.dat Example-10-1\I2C\modelsim\simprim\x_lut7\_primary.dat Example-10-1\I2C\modelsim\simprim\x_lut7 Example-10-1\I2C\modelsim\simprim\x_lut8\x_lut8_v.asm Example-10-1\I2C\modelsim\simprim\x_lut8\x_lut8_v.dat Example-10-1\I2C\modelsim\simprim\x_lut8\_primary.dat Example-10-1\I2C\modelsim\simprim\x_lut8 Example-10-1\I2C\modelsim\simprim\x_mult18x18\x_mult18x18_v.asm Example-10-1\I2C\modelsim\simprim\x_mult18x18\x_mult18x18_v.dat Example-10-1\I2C\modelsim\simprim\x_mult18x18\_primary.dat Example-10-1\I2C\modelsim\simprim\x_mult18x18 Example-10-1\I2C\modelsim\simprim\x_mult18x18s\x_mult18x18s_v.asm Example-10-1\I2C\modelsim\simprim\x_mult18x18s\x_mult18x18s_v.dat Example-10-1\I2C\modelsim\simprim\x_mult18x18s\_primary.dat Example-10-1\I2C\modelsim\simprim\x_mult18x18s Example-10-1\I2C\modelsim\simprim\x_mux2\x_mux2_v.asm Example-10-1\I2C\modelsim\simprim\x_mux2\x_mux2_v.dat Example-10-1\I2C\modelsim\simprim\x_mux2\_primary.dat Example-10-1\I2C\modelsim\simprim\x_mux2 Example-10-1\I2C\modelsim\simprim\x_muxddr\x_muxddr_v.asm Example-10-1\I2C\modelsim\simprim\x_muxddr\x_muxddr_v.dat Example-10-1\I2C\modelsim\simprim\x_muxddr\_primary.dat Example-10-1\I2C\modelsim\simprim\x_muxddr Example-10-1\I2C\modelsim\simprim\x_obufds\x_obufds_v.asm Example-10-1\I2C\modelsim\simprim\x_obufds\x_obufds_v.dat Example-10-1\I2C\modelsim\simprim\x_obufds\_primary.dat Example-10-1\I2C\modelsim\simprim\x_obufds Example-10-1\I2C\modelsim\simprim\x_obuftds\x_obuftds_v.asm Example-10-1\I2C\modelsim\simprim\x_obuftds\x_obuftds_v.dat Example-10-1\I2C\modelsim\simprim\x_obuftds\_primary.dat Example-10-1\I2C\modelsim\simprim\x_obuftds Example-10-1\I2C\modelsim\simprim\x_one\x_one_v.asm Example-10-1\I2C\modelsim\simprim\x_one\x_one_v.dat Example-10-1\I2C\modelsim\simprim\x_one\_primary.dat Example-10-1\I2C\modelsim\simprim\x_one Example-10-1\I2C\modelsim\simprim\x_opad\x_opad_v.asm Example-10-1\I2C\modelsim\simprim\x_opad\x_opad_v.dat Example-10-1\I2C\modelsim\simprim\x_opad\_primary.dat Example-10-1\I2C\modelsim\simprim\x_opad Example-10-1\I2C\modelsim\simprim\x_or16\x_or16_v.asm Example-10-1\I2C\modelsim\simprim\x_or16\x_or16_v.dat Example-10-1\I2C\modelsim\simprim\x_or16\_primary.dat Example-10-1\I2C\modelsim\simprim\x_or16 Example-10-1\I2C\modelsim\simprim\x_or2\x_or2_v.asm Example-10-1\I2C\modelsim\simprim\x_or2\x_or2_v.dat Example-10-1\I2C\modelsim\simprim\x_or2\_primary.dat Example-10-1\I2C\modelsim\simprim\x_or2 Example-10-1\I2C\modelsim\simprim\x_or3\x_or3_v.asm Example-10-1\I2C\modelsim\simprim\x_or3\x_or3_v.dat Example-10-1\I2C\modelsim\simprim\x_or3\_primary.dat Example-10-1\I2C\modelsim\simprim\x_or3 Example-10-1\I2C\modelsim\simprim\x_or32\x_or32_v.asm Example-10-1\I2C\modelsim\simprim\x_or32\x_or32_v.dat Example-10-1\I2C\modelsim\simprim\x_or32\_primary.dat Example-10-1\I2C\modelsim\simprim\x_or32 Example-10-1\I2C\modelsim\simprim\x_or4\x_or4_v.asm Example-10-1\I2C\modelsim\simprim\x_or4\x_or4_v.dat Example-10-1\I2C\modelsim\simprim\x_or4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_or4 Example-10-1\I2C\modelsim\simprim\x_or5\x_or5_v.asm Example-10-1\I2C\modelsim\simprim\x_or5\x_or5_v.dat Example-10-1\I2C\modelsim\simprim\x_or5\_primary.dat Example-10-1\I2C\modelsim\simprim\x_or5 Example-10-1\I2C\modelsim\simprim\x_or6\x_or6_v.asm Example-10-1\I2C\modelsim\simprim\x_or6\x_or6_v.dat Example-10-1\I2C\modelsim\simprim\x_or6\_primary.dat Example-10-1\I2C\modelsim\simprim\x_or6 Example-10-1\I2C\modelsim\simprim\x_or7\x_or7_v.asm Example-10-1\I2C\modelsim\simprim\x_or7\x_or7_v.dat Example-10-1\I2C\modelsim\simprim\x_or7\_primary.dat Example-10-1\I2C\modelsim\simprim\x_or7 Example-10-1\I2C\modelsim\simprim\x_or8\x_or8_v.asm Example-10-1\I2C\modelsim\simprim\x_or8\x_or8_v.dat Example-10-1\I2C\modelsim\simprim\x_or8\_primary.dat Example-10-1\I2C\modelsim\simprim\x_or8 Example-10-1\I2C\modelsim\simprim\x_or9\x_or9_v.asm Example-10-1\I2C\modelsim\simprim\x_or9\x_or9_v.dat Example-10-1\I2C\modelsim\simprim\x_or9\_primary.dat Example-10-1\I2C\modelsim\simprim\x_or9 Example-10-1\I2C\modelsim\simprim\x_pd\x_pd_v.asm Example-10-1\I2C\modelsim\simprim\x_pd\x_pd_v.dat Example-10-1\I2C\modelsim\simprim\x_pd\_primary.dat Example-10-1\I2C\modelsim\simprim\x_pd Example-10-1\I2C\modelsim\simprim\x_pu\x_pu_v.asm Example-10-1\I2C\modelsim\simprim\x_pu\x_pu_v.dat Example-10-1\I2C\modelsim\simprim\x_pu\_primary.dat Example-10-1\I2C\modelsim\simprim\x_pu Example-10-1\I2C\modelsim\simprim\x_ramb16_s1\x_ramb16_s1_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s1\x_ramb16_s1_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1 Example-10-1\I2C\modelsim\simprim\x_ramb16_s18\x_ramb16_s18_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s18\x_ramb16_s18_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s18\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s18 Example-10-1\I2C\modelsim\simprim\x_ramb16_s18_s18\x_ramb16_s18_s18_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s18_s18\x_ramb16_s18_s18_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s18_s18\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s18_s18 Example-10-1\I2C\modelsim\simprim\x_ramb16_s18_s36\x_ramb16_s18_s36_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s18_s36\x_ramb16_s18_s36_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s18_s36\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s18_s36 Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s1\x_ramb16_s1_s1_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s1\x_ramb16_s1_s1_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s1\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s1 Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s18\x_ramb16_s1_s18_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s18\x_ramb16_s1_s18_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s18\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s18 Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s2\x_ramb16_s1_s2_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s2\x_ramb16_s1_s2_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s2\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s2 Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s36\x_ramb16_s1_s36_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s36\x_ramb16_s1_s36_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s36\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s36 Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s4\x_ramb16_s1_s4_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s4\x_ramb16_s1_s4_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s4 Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s9\x_ramb16_s1_s9_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s9\x_ramb16_s1_s9_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s9\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s1_s9 Example-10-1\I2C\modelsim\simprim\x_ramb16_s2\x_ramb16_s2_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s2\x_ramb16_s2_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2 Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s18\x_ramb16_s2_s18_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s18\x_ramb16_s2_s18_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s18\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s18 Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s2\x_ramb16_s2_s2_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s2\x_ramb16_s2_s2_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s2\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s2 Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s36\x_ramb16_s2_s36_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s36\x_ramb16_s2_s36_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s36\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s36 Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s4\x_ramb16_s2_s4_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s4\x_ramb16_s2_s4_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s4 Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s9\x_ramb16_s2_s9_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s9\x_ramb16_s2_s9_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s9\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s2_s9 Example-10-1\I2C\modelsim\simprim\x_ramb16_s36\x_ramb16_s36_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s36\x_ramb16_s36_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s36\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s36 Example-10-1\I2C\modelsim\simprim\x_ramb16_s36_s36\x_ramb16_s36_s36_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s36_s36\x_ramb16_s36_s36_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s36_s36\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s36_s36 Example-10-1\I2C\modelsim\simprim\x_ramb16_s4\x_ramb16_s4_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s4\x_ramb16_s4_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s4 Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s18\x_ramb16_s4_s18_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s18\x_ramb16_s4_s18_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s18\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s18 Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s36\x_ramb16_s4_s36_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s36\x_ramb16_s4_s36_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s36\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s36 Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s4\x_ramb16_s4_s4_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s4\x_ramb16_s4_s4_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s4 Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s9\x_ramb16_s4_s9_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s9\x_ramb16_s4_s9_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s9\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s4_s9 Example-10-1\I2C\modelsim\simprim\x_ramb16_s9\x_ramb16_s9_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s9\x_ramb16_s9_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s9\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s9 Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s18\x_ramb16_s9_s18_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s18\x_ramb16_s9_s18_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s18\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s18 Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s36\x_ramb16_s9_s36_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s36\x_ramb16_s9_s36_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s36\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s36 Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s9\x_ramb16_s9_s9_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s9\x_ramb16_s9_s9_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s9\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb16_s9_s9 Example-10-1\I2C\modelsim\simprim\x_ramb4_s1\x_ramb4_s1_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s1\x_ramb4_s1_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1 Example-10-1\I2C\modelsim\simprim\x_ramb4_s16\x_ramb4_s16_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s16\x_ramb4_s16_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s16\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s16 Example-10-1\I2C\modelsim\simprim\x_ramb4_s16_s16\x_ramb4_s16_s16_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s16_s16\x_ramb4_s16_s16_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s16_s16\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s16_s16 Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s1\x_ramb4_s1_s1_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s1\x_ramb4_s1_s1_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s1\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s1 Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s16\x_ramb4_s1_s16_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s16\x_ramb4_s1_s16_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s16\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s16 Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s2\x_ramb4_s1_s2_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s2\x_ramb4_s1_s2_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s2\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s2 Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s4\x_ramb4_s1_s4_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s4\x_ramb4_s1_s4_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s4 Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s8\x_ramb4_s1_s8_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s8\x_ramb4_s1_s8_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s8\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s1_s8 Example-10-1\I2C\modelsim\simprim\x_ramb4_s2\x_ramb4_s2_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s2\x_ramb4_s2_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s2\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s2 Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s16\x_ramb4_s2_s16_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s16\x_ramb4_s2_s16_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s16\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s16 Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s2\x_ramb4_s2_s2_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s2\x_ramb4_s2_s2_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s2\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s2 Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s4\x_ramb4_s2_s4_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s4\x_ramb4_s2_s4_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s4 Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s8\x_ramb4_s2_s8_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s8\x_ramb4_s2_s8_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s8\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s2_s8 Example-10-1\I2C\modelsim\simprim\x_ramb4_s4\x_ramb4_s4_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s4\x_ramb4_s4_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s4 Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s16\x_ramb4_s4_s16_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s16\x_ramb4_s4_s16_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s16\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s16 Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s4\x_ramb4_s4_s4_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s4\x_ramb4_s4_s4_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s4 Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s8\x_ramb4_s4_s8_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s8\x_ramb4_s4_s8_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s8\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s4_s8 Example-10-1\I2C\modelsim\simprim\x_ramb4_s8\x_ramb4_s8_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s8\x_ramb4_s8_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s8\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s8 Example-10-1\I2C\modelsim\simprim\x_ramb4_s8_s16\x_ramb4_s8_s16_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s8_s16\x_ramb4_s8_s16_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s8_s16\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s8_s16 Example-10-1\I2C\modelsim\simprim\x_ramb4_s8_s8\x_ramb4_s8_s8_v.asm Example-10-1\I2C\modelsim\simprim\x_ramb4_s8_s8\x_ramb4_s8_s8_v.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s8_s8\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramb4_s8_s8 Example-10-1\I2C\modelsim\simprim\x_ramd16\x_ramd16_v.asm Example-10-1\I2C\modelsim\simprim\x_ramd16\x_ramd16_v.dat Example-10-1\I2C\modelsim\simprim\x_ramd16\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramd16 Example-10-1\I2C\modelsim\simprim\x_ramd32\x_ramd32_v.asm Example-10-1\I2C\modelsim\simprim\x_ramd32\x_ramd32_v.dat Example-10-1\I2C\modelsim\simprim\x_ramd32\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramd32 Example-10-1\I2C\modelsim\simprim\x_ramd64\x_ramd64_v.asm Example-10-1\I2C\modelsim\simprim\x_ramd64\x_ramd64_v.dat Example-10-1\I2C\modelsim\simprim\x_ramd64\_primary.dat Example-10-1\I2C\modelsim\simprim\x_ramd64 Example-10-1\I2C\modelsim\simprim\x_rams128\x_rams128_v.asm Example-10-1\I2C\modelsim\simprim\x_rams128\x_rams128_v.dat Example-10-1\I2C\modelsim\simprim\x_rams128\_primary.dat Example-10-1\I2C\modelsim\simprim\x_rams128 Example-10-1\I2C\modelsim\simprim\x_rams16\x_rams16_v.asm Example-10-1\I2C\modelsim\simprim\x_rams16\x_rams16_v.dat Example-10-1\I2C\modelsim\simprim\x_rams16\_primary.dat Example-10-1\I2C\modelsim\simprim\x_rams16 Example-10-1\I2C\modelsim\simprim\x_rams32\x_rams32_v.asm Example-10-1\I2C\modelsim\simprim\x_rams32\x_rams32_v.dat Example-10-1\I2C\modelsim\simprim\x_rams32\_primary.dat Example-10-1\I2C\modelsim\simprim\x_rams32 Example-10-1\I2C\modelsim\simprim\x_rams64\x_rams64_v.asm Example-10-1\I2C\modelsim\simprim\x_rams64\x_rams64_v.dat Example-10-1\I2C\modelsim\simprim\x_rams64\_primary.dat Example-10-1\I2C\modelsim\simprim\x_rams64 Example-10-1\I2C\modelsim\simprim\x_roc\x_roc_v.asm Example-10-1\I2C\modelsim\simprim\x_roc\x_roc_v.dat Example-10-1\I2C\modelsim\simprim\x_roc\_primary.dat Example-10-1\I2C\modelsim\simprim\x_roc Example-10-1\I2C\modelsim\simprim\x_rocbuf\x_rocbuf_v.asm Example-10-1\I2C\modelsim\simprim\x_rocbuf\x_rocbuf_v.dat Example-10-1\I2C\modelsim\simprim\x_rocbuf\_primary.dat Example-10-1\I2C\modelsim\simprim\x_rocbuf Example-10-1\I2C\modelsim\simprim\x_sff\x_sff_v.asm Example-10-1\I2C\modelsim\simprim\x_sff\x_sff_v.dat Example-10-1\I2C\modelsim\simprim\x_sff\_primary.dat Example-10-1\I2C\modelsim\simprim\x_sff Example-10-1\I2C\modelsim\simprim\x_srl16e\x_srl16e_v.asm Example-10-1\I2C\modelsim\simprim\x_srl16e\x_srl16e_v.dat Example-10-1\I2C\modelsim\simprim\x_srl16e\_primary.dat Example-10-1\I2C\modelsim\simprim\x_srl16e Example-10-1\I2C\modelsim\simprim\x_srlc16e\x_srlc16e_v.asm Example-10-1\I2C\modelsim\simprim\x_srlc16e\x_srlc16e_v.dat Example-10-1\I2C\modelsim\simprim\x_srlc16e\_primary.dat Example-10-1\I2C\modelsim\simprim\x_srlc16e Example-10-1\I2C\modelsim\simprim\x_suh\x_suh_v.asm Example-10-1\I2C\modelsim\simprim\x_suh\x_suh_v.dat Example-10-1\I2C\modelsim\simprim\x_suh\_primary.dat Example-10-1\I2C\modelsim\simprim\x_suh Example-10-1\I2C\modelsim\simprim\x_toc\x_toc_v.asm Example-10-1\I2C\modelsim\simprim\x_toc\x_toc_v.dat Example-10-1\I2C\modelsim\simprim\x_toc\_primary.dat Example-10-1\I2C\modelsim\simprim\x_toc Example-10-1\I2C\modelsim\simprim\x_tocbuf\x_tocbuf_v.asm Example-10-1\I2C\modelsim\simprim\x_tocbuf\x_tocbuf_v.dat Example-10-1\I2C\modelsim\simprim\x_tocbuf\_primary.dat Example-10-1\I2C\modelsim\simprim\x_tocbuf Example-10-1\I2C\modelsim\simprim\x_tri\x_tri_v.asm Example-10-1\I2C\modelsim\simprim\x_tri\x_tri_v.dat Example-10-1\I2C\modelsim\simprim\x_tri\_primary.dat Example-10-1\I2C\modelsim\simprim\x_tri Example-10-1\I2C\modelsim\simprim\x_tri_pp\x_tri_pp_v.asm Example-10-1\I2C\modelsim\simprim\x_tri_pp\x_tri_pp_v.dat Example-10-1\I2C\modelsim\simprim\x_tri_pp\_primary.dat Example-10-1\I2C\modelsim\simprim\x_tri_pp Example-10-1\I2C\modelsim\simprim\x_upad\x_upad_v.asm Example-10-1\I2C\modelsim\simprim\x_upad\x_upad_v.dat Example-10-1\I2C\modelsim\simprim\x_upad\_primary.dat Example-10-1\I2C\modelsim\simprim\x_upad Example-10-1\I2C\modelsim\simprim\x_xor16\x_xor16_v.asm Example-10-1\I2C\modelsim\simprim\x_xor16\x_xor16_v.dat Example-10-1\I2C\modelsim\simprim\x_xor16\_primary.dat Example-10-1\I2C\modelsim\simprim\x_xor16 Example-10-1\I2C\modelsim\simprim\x_xor2\x_xor2_v.asm Example-10-1\I2C\modelsim\simprim\x_xor2\x_xor2_v.dat Example-10-1\I2C\modelsim\simprim\x_xor2\_primary.dat Example-10-1\I2C\modelsim\simprim\x_xor2 Example-10-1\I2C\modelsim\simprim\x_xor3\x_xor3_v.asm Example-10-1\I2C\modelsim\simprim\x_xor3\x_xor3_v.dat Example-10-1\I2C\modelsim\simprim\x_xor3\_primary.dat Example-10-1\I2C\modelsim\simprim\x_xor3 Example-10-1\I2C\modelsim\simprim\x_xor32\x_xor32_v.asm Example-10-1\I2C\modelsim\simprim\x_xor32\x_xor32_v.dat Example-10-1\I2C\modelsim\simprim\x_xor32\_primary.dat Example-10-1\I2C\modelsim\simprim\x_xor32 Example-10-1\I2C\modelsim\simprim\x_xor4\x_xor4_v.asm Example-10-1\I2C\modelsim\simprim\x_xor4\x_xor4_v.dat Example-10-1\I2C\modelsim\simprim\x_xor4\_primary.dat Example-10-1\I2C\modelsim\simprim\x_xor4 Example-10-1\I2C\modelsim\simprim\x_xor5\x_xor5_v.asm Example-10-1\I2C\modelsim\simprim\x_xor5\x_xor5_v.dat Example-10-1\I2C\modelsim\simprim\x_xor5\_primary.dat Example-10-1\I2C\modelsim\simprim\x_xor5 Example-10-1\I2C\modelsim\simprim\x_xor6\x_xor6_v.asm Example-10-1\I2C\modelsim\simprim\x_xor6\x_xor6_v.dat Example-10-1\I2C\modelsim\simprim\x_xor6\_primary.dat Example-10-1\I2C\modelsim\simprim\x_xor6 Example-10-1\I2C\modelsim\simprim\x_xor7\x_xor7_v.asm Example-10-1\I2C\modelsim\simprim\x_xor7\x_xor7_v.dat Example-10-1\I2C\modelsim\simprim\x_xor7\_primary.dat Example-10-1\I2C\modelsim\simprim\x_xor7 Example-10-1\I2C\modelsim\simprim\x_xor8\x_xor8_v.asm Example-10-1\I2C\modelsim\simprim\x_xor8\x_xor8_v.dat Example-10-1\I2C\modelsim\simprim\x_xor8\_primary.dat Example-10-1\I2C\modelsim\simprim\x_xor8 Example-10-1\I2C\modelsim\simprim\x_zero\x_zero_v.asm Example-10-1\I2C\modelsim\simprim\x_zero\x_zero_v.dat Example-10-1\I2C\modelsim\simprim\x_zero\_primary.dat Example-10-1\I2C\modelsim\simprim\x_zero Example-10-1\I2C\modelsim\simprim\_info Example-10-1\I2C\modelsim\simprim Example-10-1\I2C\modelsim\transcript Example-10-1\I2C\modelsim\vital2000\math_complex\body.asm Example-10-1\I2C\modelsim\vital2000\math_complex\body.asm64 Example-10-1\I2C\modelsim\vital2000\math_complex\body.dat Example-10-1\I2C\modelsim\vital2000\math_complex\body.psm Example-10-1\I2C\modelsim\vital2000\math_complex\_primary.dat Example-10-1\I2C\modelsim\vital2000\math_complex\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\math_complex\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\math_complex\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\math_complex Example-10-1\I2C\modelsim\vital2000\math_real\body.asm Example-10-1\I2C\modelsim\vital2000\math_real\body.asm64 Example-10-1\I2C\modelsim\vital2000\math_real\body.dat Example-10-1\I2C\modelsim\vital2000\math_real\body.psm Example-10-1\I2C\modelsim\vital2000\math_real\_primary.dat Example-10-1\I2C\modelsim\vital2000\math_real\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\math_real\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\math_real\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\math_real Example-10-1\I2C\modelsim\vital2000\numeric_bit\body.asm Example-10-1\I2C\modelsim\vital2000\numeric_bit\body.asm64 Example-10-1\I2C\modelsim\vital2000\numeric_bit\body.dat Example-10-1\I2C\modelsim\vital2000\numeric_bit\body.psm Example-10-1\I2C\modelsim\vital2000\numeric_bit\_primary.dat Example-10-1\I2C\modelsim\vital2000\numeric_bit\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\numeric_bit\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\numeric_bit\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\numeric_bit Example-10-1\I2C\modelsim\vital2000\numeric_std\body.asm Example-10-1\I2C\modelsim\vital2000\numeric_std\body.asm64 Example-10-1\I2C\modelsim\vital2000\numeric_std\body.dat Example-10-1\I2C\modelsim\vital2000\numeric_std\body.psm Example-10-1\I2C\modelsim\vital2000\numeric_std\_primary.dat Example-10-1\I2C\modelsim\vital2000\numeric_std\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\numeric_std\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\numeric_std\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\numeric_std Example-10-1\I2C\modelsim\vital2000\std_logic_1164\body.asm Example-10-1\I2C\modelsim\vital2000\std_logic_1164\body.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_1164\body.dat Example-10-1\I2C\modelsim\vital2000\std_logic_1164\body.psm Example-10-1\I2C\modelsim\vital2000\std_logic_1164\_primary.dat Example-10-1\I2C\modelsim\vital2000\std_logic_1164\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\std_logic_1164\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_1164\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\std_logic_1164 Example-10-1\I2C\modelsim\vital2000\std_logic_arith\body.asm Example-10-1\I2C\modelsim\vital2000\std_logic_arith\body.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_arith\body.dat Example-10-1\I2C\modelsim\vital2000\std_logic_arith\body.psm Example-10-1\I2C\modelsim\vital2000\std_logic_arith\_primary.dat Example-10-1\I2C\modelsim\vital2000\std_logic_arith\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\std_logic_arith\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_arith\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\std_logic_arith Example-10-1\I2C\modelsim\vital2000\std_logic_misc\body.asm Example-10-1\I2C\modelsim\vital2000\std_logic_misc\body.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_misc\body.dat Example-10-1\I2C\modelsim\vital2000\std_logic_misc\body.psm Example-10-1\I2C\modelsim\vital2000\std_logic_misc\_primary.dat Example-10-1\I2C\modelsim\vital2000\std_logic_misc\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\std_logic_misc\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_misc\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\std_logic_misc Example-10-1\I2C\modelsim\vital2000\std_logic_signed\body.asm Example-10-1\I2C\modelsim\vital2000\std_logic_signed\body.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_signed\body.dat Example-10-1\I2C\modelsim\vital2000\std_logic_signed\body.psm Example-10-1\I2C\modelsim\vital2000\std_logic_signed\_primary.dat Example-10-1\I2C\modelsim\vital2000\std_logic_signed\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\std_logic_signed\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_signed\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\std_logic_signed Example-10-1\I2C\modelsim\vital2000\std_logic_textio\body.asm Example-10-1\I2C\modelsim\vital2000\std_logic_textio\body.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_textio\body.dat Example-10-1\I2C\modelsim\vital2000\std_logic_textio\body.psm Example-10-1\I2C\modelsim\vital2000\std_logic_textio\_primary.dat Example-10-1\I2C\modelsim\vital2000\std_logic_textio\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\std_logic_textio\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_textio\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\std_logic_textio Example-10-1\I2C\modelsim\vital2000\std_logic_unsigned\body.asm Example-10-1\I2C\modelsim\vital2000\std_logic_unsigned\body.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_unsigned\body.dat Example-10-1\I2C\modelsim\vital2000\std_logic_unsigned\body.psm Example-10-1\I2C\modelsim\vital2000\std_logic_unsigned\_primary.dat Example-10-1\I2C\modelsim\vital2000\std_logic_unsigned\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\std_logic_unsigned\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\std_logic_unsigned\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\std_logic_unsigned Example-10-1\I2C\modelsim\vital2000\vital_memory\body.asm Example-10-1\I2C\modelsim\vital2000\vital_memory\body.asm64 Example-10-1\I2C\modelsim\vital2000\vital_memory\body.dat Example-10-1\I2C\modelsim\vital2000\vital_memory\body.psm Example-10-1\I2C\modelsim\vital2000\vital_memory\_primary.dat Example-10-1\I2C\modelsim\vital2000\vital_memory\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\vital_memory\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\vital_memory\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\vital_memory Example-10-1\I2C\modelsim\vital2000\vital_primitives\body.asm Example-10-1\I2C\modelsim\vital2000\vital_primitives\body.asm64 Example-10-1\I2C\modelsim\vital2000\vital_primitives\body.dat Example-10-1\I2C\modelsim\vital2000\vital_primitives\body.psm Example-10-1\I2C\modelsim\vital2000\vital_primitives\_primary.dat Example-10-1\I2C\modelsim\vital2000\vital_primitives\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\vital_primitives\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\vital_primitives\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\vital_primitives Example-10-1\I2C\modelsim\vital2000\vital_timing\body.asm Example-10-1\I2C\modelsim\vital2000\vital_timing\body.asm64 Example-10-1\I2C\modelsim\vital2000\vital_timing\body.dat Example-10-1\I2C\modelsim\vital2000\vital_timing\body.psm Example-10-1\I2C\modelsim\vital2000\vital_timing\_primary.dat Example-10-1\I2C\modelsim\vital2000\vital_timing\_vhdl.asm Example-10-1\I2C\modelsim\vital2000\vital_timing\_vhdl.asm64 Example-10-1\I2C\modelsim\vital2000\vital_timing\_vhdl.psm Example-10-1\I2C\modelsim\vital2000\vital_timing Example-10-1\I2C\modelsim\vital2000\_info Example-10-1\I2C\modelsim\vital2000 Example-10-1\I2C\modelsim\vsim.wlf Example-10-1\I2C\modelsim\work\@a@t24@c02\verilog.asm Example-10-1\I2C\modelsim\work\@a@t24@c02\_primary.dat Example-10-1\I2C\modelsim\work\@a@t24@c02\_primary.vhd Example-10-1\I2C\modelsim\work\@a@t24@c02 Example-10-1\I2C\modelsim\work\@p@u@l@l@u@p\verilog.asm Example-10-1\I2C\modelsim\work\@p@u@l@l@u@p\_primary.dat Example-10-1\I2C\modelsim\work\@p@u@l@l@u@p\_primary.vhd Example-10-1\I2C\modelsim\work\@p@u@l@l@u@p Example-10-1\I2C\modelsim\work\i2c\structure.asm Example-10-1\I2C\modelsim\work\i2c\structure.dat Example-10-1\I2C\modelsim\work\i2c\_primary.dat Example-10-1\I2C\modelsim\work\i2c Example-10-1\I2C\modelsim\work\tb\verilog.asm Example-10-1\I2C\modelsim\work\tb\_primary.dat Example-10-1\I2C\modelsim\work\tb\_primary.vhd Example-10-1\I2C\modelsim\work\tb Example-10-1\I2C\modelsim\work\_info Example-10-1\I2C\modelsim\work Example-10-1\I2C\modelsim Example-10-1\I2C\source\At24c02.v Example-10-1\I2C\source\i2c.vhd Example-10-1\I2C\source\i2c_control.vhd Example-10-1\I2C\source\pullup.v Example-10-1\I2C\source\shift.vhd Example-10-1\I2C\source\tb.v Example-10-1\I2C\source\uc_interface.vhd Example-10-1\I2C\source\upcnt4.vhd Example-10-1\I2C\source Example-10-1\I2C\synplify\I2C_synplify\i2c_synplify.edf Example-10-1\I2C\synplify\I2C_synplify\i2c_synplify.fse Example-10-1\I2C\synplify\I2C_synplify\i2c_synplify.ncf Example-10-1\I2C\synplify\I2C_synplify\i2c_synplify.plg Example-10-1\I2C\synplify\I2C_synplify\i2c_synplify.srd Example-10-1\I2C\synplify\I2C_synplify\i2c_synplify.srm Example-10-1\I2C\synplify\I2C_synplify\i2c_synplify.srr Example-10-1\I2C\synplify\I2C_synplify\i2c_synplify.srs Example-10-1\I2C\synplify\I2C_synplify\i2c_synplify.tlg Example-10-1\I2C\synplify\I2C_synplify\i2c_synplify.vhd Example-10-1\I2C\synplify\I2C_synplify\traplog.tlg Example-10-1\I2C\synplify\I2C_synplify\uc_interface.edf Example-10-1\I2C\synplify\I2C_synplify\uc_interface.fse Example-10-1\I2C\synplify\I2C_synplify\uc_interface.ncf Example-10-1\I2C\synplify\I2C_synplify\uc_interface.plg Example-10-1\I2C\synplify\I2C_synplify\uc_interface.srd Example-10-1\I2C\synplify\I2C_synplify\uc_interface.srm Example-10-1\I2C\synplify\I2C_synplify\uc_interface.srr Example-10-1\I2C\synplify\I2C_synplify\uc_interface.srs Example-10-1\I2C\synplify\I2C_synplify\uc_interface.tlg Example-10-1\I2C\synplify\I2C_synplify Example-10-1\I2C\synplify\I2C_syplify.prd Example-10-1\I2C\synplify\I2C_syplify.prj Example-10-1\I2C\synplify Example-10-1\I2C\xst\I2C\.untf Example-10-1\I2C\xst\I2C\automake.log Example-10-1\I2C\xst\I2C\coregen.log Example-10-1\I2C\xst\I2C\coregen.prj Example-10-1\I2C\xst\I2C\i2c.bld Example-10-1\I2C\xst\I2C\i2c.cmd_log Example-10-1\I2C\xst\I2C\I2C.dhp Example-10-1\I2C\xst\I2C\i2c.lso Example-10-1\I2C\xst\I2C\i2c.map_nlf Example-10-1\I2C\xst\I2C\i2c.mrp Example-10-1\I2C\xst\I2C\i2c.nc1 Example-10-1\I2C\xst\I2C\i2c.ncd Example-10-1\I2C\xst\I2C\i2c.ngc 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Example-8-1\Modular_Design\Imp_modules\module_b\netlist.lst Example-8-1\Modular_Design\Imp_modules\module_b\top.bld Example-8-1\Modular_Design\Imp_modules\module_b\top.mrp Example-8-1\Modular_Design\Imp_modules\module_b\top.ncd Example-8-1\Modular_Design\Imp_modules\module_b\top.ngd Example-8-1\Modular_Design\Imp_modules\module_b\top.ngm Example-8-1\Modular_Design\Imp_modules\module_b\top.ngo Example-8-1\Modular_Design\Imp_modules\module_b\top.pcf Example-8-1\Modular_Design\Imp_modules\module_b\top_ngdbuild.nav Example-8-1\Modular_Design\Imp_modules\module_b\top_routed.dly Example-8-1\Modular_Design\Imp_modules\module_b\top_routed.ncd Example-8-1\Modular_Design\Imp_modules\module_b\top_routed.pad Example-8-1\Modular_Design\Imp_modules\module_b\top_routed.par Example-8-1\Modular_Design\Imp_modules\module_b\top_routed.twr Example-8-1\Modular_Design\Imp_modules\module_b\top_routed.xpi Example-8-1\Modular_Design\Imp_modules\module_b Example-8-1\Modular_Design\Imp_modules\module_c\module_c.edf Example-8-1\Modular_Design\Imp_modules\module_c\module_c.ngo Example-8-1\Modular_Design\Imp_modules\module_c\module_c.ucf Example-8-1\Modular_Design\Imp_modules\module_c\netlist.lst Example-8-1\Modular_Design\Imp_modules\module_c\top.bld Example-8-1\Modular_Design\Imp_modules\module_c\top.mrp Example-8-1\Modular_Design\Imp_modules\module_c\top.ncd Example-8-1\Modular_Design\Imp_modules\module_c\top.ngd Example-8-1\Modular_Design\Imp_modules\module_c\top.ngm Example-8-1\Modular_Design\Imp_modules\module_c\top.ngo Example-8-1\Modular_Design\Imp_modules\module_c\top.pcf Example-8-1\Modular_Design\Imp_modules\module_c\top_ngdbuild.nav Example-8-1\Modular_Design\Imp_modules\module_c\top_routed.dly Example-8-1\Modular_Design\Imp_modules\module_c\top_routed.ncd Example-8-1\Modular_Design\Imp_modules\module_c\top_routed.pad Example-8-1\Modular_Design\Imp_modules\module_c\top_routed.par Example-8-1\Modular_Design\Imp_modules\module_c\top_routed.twr Example-8-1\Modular_Design\Imp_modules\module_c\top_routed.xpi Example-8-1\Modular_Design\Imp_modules\module_c Example-8-1\Modular_Design\Imp_modules Example-8-1\Modular_Design\Imp_top\netlist.lst Example-8-1\Modular_Design\Imp_top\ngd2ver.log Example-8-1\Modular_Design\Imp_top\ngd2vhdl.log Example-8-1\Modular_Design\Imp_top\top.alf Example-8-1\Modular_Design\Imp_top\top.bld Example-8-1\Modular_Design\Imp_top\top.cel Example-8-1\Modular_Design\Imp_top\top.edf Example-8-1\Modular_Design\Imp_top\top.fnf Example-8-1\Modular_Design\Imp_top\top.mrp Example-8-1\Modular_Design\Imp_top\top.ncd Example-8-1\Modular_Design\Imp_top\top.nga Example-8-1\Modular_Design\Imp_top\top.ngd Example-8-1\Modular_Design\Imp_top\top.ngm Example-8-1\Modular_Design\Imp_top\top.ngo Example-8-1\Modular_Design\Imp_top\top.pcf Example-8-1\Modular_Design\Imp_top\top.sdf Example-8-1\Modular_Design\Imp_top\top.ucf Example-8-1\Modular_Design\Imp_top\top.v Example-8-1\Modular_Design\Imp_top\top.vhd Example-8-1\Modular_Design\Imp_top\top_constraints.ucf Example-8-1\Modular_Design\Imp_top\top_ngdbuild.nav Example-8-1\Modular_Design\Imp_top\top_routed.dly Example-8-1\Modular_Design\Imp_top\top_routed.grf Example-8-1\Modular_Design\Imp_top\top_routed.ncd Example-8-1\Modular_Design\Imp_top\top_routed.pad Example-8-1\Modular_Design\Imp_top\top_routed.par Example-8-1\Modular_Design\Imp_top\top_routed.twr Example-8-1\Modular_Design\Imp_top\top_routed.xpi Example-8-1\Modular_Design\Imp_top\_fplan.ucf Example-8-1\Modular_Design\Imp_top Example-8-1\Modular_Design\PIMs\module_a\module_a.ncd Example-8-1\Modular_Design\PIMs\module_a\module_a.ngc Example-8-1\Modular_Design\PIMs\module_a\module_a.ngm Example-8-1\Modular_Design\PIMs\module_a\top.ngc Example-8-1\Modular_Design\PIMs\module_a Example-8-1\Modular_Design\PIMs\module_b\module_b.ncd Example-8-1\Modular_Design\PIMs\module_b\module_b.ngc Example-8-1\Modular_Design\PIMs\module_b\module_b.ngm Example-8-1\Modular_Design\PIMs\module_b\top.ngc Example-8-1\Modular_Design\PIMs\module_b Example-8-1\Modular_Design\PIMs\module_c\module_c.ncd Example-8-1\Modular_Design\PIMs\module_c\module_c.ngc Example-8-1\Modular_Design\PIMs\module_c\module_c.ngm Example-8-1\Modular_Design\PIMs\module_c\top.ngc Example-8-1\Modular_Design\PIMs\module_c Example-8-1\Modular_Design\PIMs Example-8-1\Modular_Design\syn_modules\module_a\module_a.v Example-8-1\Modular_Design\syn_modules\module_a\rev_1\module_a.edf Example-8-1\Modular_Design\syn_modules\module_a\rev_1\module_a.fse Example-8-1\Modular_Design\syn_modules\module_a\rev_1\module_a.ncf Example-8-1\Modular_Design\syn_modules\module_a\rev_1\module_a.plg Example-8-1\Modular_Design\syn_modules\module_a\rev_1\module_a.srd Example-8-1\Modular_Design\syn_modules\module_a\rev_1\module_a.srm Example-8-1\Modular_Design\syn_modules\module_a\rev_1\module_a.srr Example-8-1\Modular_Design\syn_modules\module