文件名称:SPI

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.83mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • l***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

基于verilog语言的 SPI接口实现. 有很好的说明.-Verilog language based SPI interface. Have a good descr iption.
相关搜索: spi

(系统自动生成,下载前可以参看下载内容)

下载文件列表

SPI

...\DOC

...\...\spi.pdf_rev=1.pdf

...\...\x-msword.doc

...\RTL

...\...\bench.vcd

...\...\modelsim.ini

...\...\rtl.fl

...\...\run_sim.txt

...\...\sim.fl

...\...\spi_clgen.v

...\...\spi_defines.v

...\...\spi_shift.v

...\...\spi_slave_model.v

...\...\spi_top

...\...\spi_top.v

...\...\.......\db

...\...\.......\..\spi_top.asm.qmsg

...\...\.......\..\spi_top.asm_labs.ddb

...\...\.......\..\spi_top.cbx.xml

...\...\.......\..\spi_top.cmp.bpm

...\...\.......\..\spi_top.cmp.cdb

...\...\.......\..\spi_top.cmp.ecobp

...\...\.......\..\spi_top.cmp.hdb

...\...\.......\..\spi_top.cmp.logdb

...\...\.......\..\spi_top.cmp.rdb

...\...\.......\..\spi_top.cmp.tdb

...\...\.......\..\spi_top.cmp0.ddb

...\...\.......\..\spi_top.cmp_bb.cdb

...\...\.......\..\spi_top.cmp_bb.hdb

...\...\.......\..\spi_top.cmp_bb.logdb

...\...\.......\..\spi_top.cmp_bb.rcf

...\...\.......\..\spi_top.dbp

...\...\.......\..\spi_top.db_info

...\...\.......\..\spi_top.eco.cdb

...\...\.......\..\spi_top.fit.qmsg

...\...\.......\..\spi_top.hier_info

...\...\.......\..\spi_top.hif

...\...\.......\..\spi_top.map.bpm

...\...\.......\..\spi_top.map.cdb

...\...\.......\..\spi_top.map.ecobp

...\...\.......\..\spi_top.map.hdb

...\...\.......\..\spi_top.map.logdb

...\...\.......\..\spi_top.map.qmsg

...\...\.......\..\spi_top.map_bb.cdb

...\...\.......\..\spi_top.map_bb.hdb

...\...\.......\..\spi_top.map_bb.logdb

...\...\.......\..\spi_top.merge.qmsg

...\...\.......\..\spi_top.pre_map.cdb

...\...\.......\..\spi_top.pre_map.hdb

...\...\.......\..\spi_top.psp

...\...\.......\..\spi_top.pss

...\...\.......\..\spi_top.rtlv.hdb

...\...\.......\..\spi_top.rtlv_sg.cdb

...\...\.......\..\spi_top.rtlv_sg_swap.cdb

...\...\.......\..\spi_top.sgdiff.cdb

...\...\.......\..\spi_top.sgdiff.hdb

...\...\.......\..\spi_top.signalprobe.cdb

...\...\.......\..\spi_top.sld_design_entry.sci

...\...\.......\..\spi_top.sld_design_entry_dsc.sci

...\...\.......\..\spi_top.syn_hier_info

...\...\.......\..\spi_top.tan.qmsg

...\...\.......\spi_top.asm.rpt

...\...\.......\spi_top.done

...\...\.......\spi_top.fit.rpt

...\...\.......\spi_top.fit.summary

...\...\.......\spi_top.flow.rpt

...\...\.......\spi_top.map.rpt

...\...\.......\spi_top.map.smsg

...\...\.......\spi_top.map.summary

...\...\.......\spi_top.merge.rpt

...\...\.......\spi_top.pin

...\...\.......\spi_top.pof

...\...\.......\spi_top.qpf

...\...\.......\spi_top.qsf

...\...\.......\spi_top.qws

...\...\.......\spi_top.sof

...\...\.......\spi_top.tan.rpt

...\...\.......\spi_top.tan.summary

...\...\tb_spi_top.v

...\...\timescale.v

...\...\wb_master_model.v

...\...\work

...\...\....\spi_clgen

...\...\....\.........\verilog.asm

...\...\....\.........\_primary.dat

...\...\....\.........\_primary.vhd

...\...\....\spi_shift

...\...\....\.........\verilog.asm

...\...\....\.........\_primary.dat

...\...\....\.........\_primary.vhd

...\...\....\spi_slave_model

...\...\....\...............\verilog.asm

...\...\....\...............\_primary.dat

...\...\....\...............\_primary.vhd

...\...\....\spi_top

...\...\....\.......\verilog.asm

...\...\....\.......\_primary.dat

...\...\....\.......\_primary.vhd

...\...\....\tb_spi_top

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