文件名称:bpsk_fpga
介绍说明－－下载内容均来自于网络，请自行研究使用
在FPGA上实现BPSK信号的解调，全部用VHDL语言编写，非常实用。-Implemented on the FPGA BPSK signal demodulation, all with the VHDL language, very useful.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
bpsk_fpga\bpsk_fpga.asm.rpt
.........\bpsk_fpga.bdf
.........\bpsk_fpga.bsf
.........\bpsk_fpga.cdf
.........\bpsk_fpga.done
.........\bpsk_fpga.dpf
.........\bpsk_fpga.fit.eqn
.........\bpsk_fpga.fit.rpt
.........\bpsk_fpga.fit.smsg
.........\bpsk_fpga.fit.summary
.........\bpsk_fpga.flow.rpt
.........\bpsk_fpga.map.eqn
.........\bpsk_fpga.map.rpt
.........\bpsk_fpga.map.summary
.........\bpsk_fpga.pin
.........\bpsk_fpga.pof
.........\bpsk_fpga.qpf
.........\bpsk_fpga.qsf
.........\bpsk_fpga.qws
.........\bpsk_fpga.sim.rpt
.........\bpsk_fpga.sof
.........\bpsk_fpga.tan.rpt
.........\bpsk_fpga.tan.summary
.........\bpsk_fpga_assignment_defaults.qdf
.........\cmp_state.ini
.........\Decision.bsf
.........\DelayOyx.bsf
.........\fenpin.bsf
.........\PLL_CLK.bsf
.........\PLL_CLK.cmp
.........\PLL_CLK.ppf
.........\PLL_CLK.vhd
.........\PLL_CLK_wave0.jpg
.........\PLL_CLK_waveforms.html
.........\pulse.bsf
.........\RemoveBurr.bsf
.........\stable.bsf
.........\wave\bpsk_fpga.vwf
.........\....\Decision.vwf
.........\....\fenpin.vwf
.........\....\fm_decode.vwf
.........\....\pulse.vwf
.........\....\removeburr.vwf
.........\....\signalsyn.vwf
.........\....\stable.vwf
.........\source\Decision.vhd
.........\......\DelayOyx.vhd
.........\......\div_clk.vhd
.........\......\fenpin.vhd
.........\......\FM_Decode.vhd
.........\......\oyxtemp.bdf
.........\......\pulse.vhd
.........\......\RemoveBurr.vhd
.........\......\SignalSyn.bdf
.........\......\SignSyn_book.bdf
.........\......\SignSyn_book.bsf
.........\......\stable.vhd
.........\db\add_sub_n2i.tdf
.........\..\bpsk_fpga.analyze_file.qmsg
.........\..\bpsk_fpga.asm.qmsg
.........\..\bpsk_fpga.asm_labs.ddb
.........\..\bpsk_fpga.cbx.xml
.........\..\bpsk_fpga.cmp.cdb
.........\..\bpsk_fpga.cmp.hdb
.........\..\bpsk_fpga.cmp.kpt
.........\..\bpsk_fpga.cmp.logdb
.........\..\bpsk_fpga.cmp.rdb
.........\..\bpsk_fpga.cmp.tdb
.........\..\bpsk_fpga.cmp0.ddb
.........\..\bpsk_fpga.cmp2.ddb
.........\..\bpsk_fpga.dbp
.........\..\bpsk_fpga.db_info
.........\..\bpsk_fpga.eco.cdb
.........\..\bpsk_fpga.eds_overflow
.........\..\bpsk_fpga.fit.qmsg
.........\..\bpsk_fpga.hier_info
.........\..\bpsk_fpga.hif
.........\..\bpsk_fpga.map.cdb
.........\..\bpsk_fpga.map.hdb
.........\..\bpsk_fpga.map.logdb
.........\..\bpsk_fpga.map.qmsg
.........\..\bpsk_fpga.pre_map.cdb
.........\..\bpsk_fpga.pre_map.hdb
.........\..\bpsk_fpga.psp
.........\..\bpsk_fpga.rtlv.hdb
.........\..\bpsk_fpga.rtlv_sg.cdb
.........\..\bpsk_fpga.rtlv_sg_swap.cdb
.........\..\bpsk_fpga.sgdiff.cdb
.........\..\bpsk_fpga.sgdiff.hdb
.........\..\bpsk_fpga.signalprobe.cdb
.........\..\bpsk_fpga.sim.hdb
.........\..\bpsk_fpga.sim.qmsg
.........\..\bpsk_fpga.sim.rdb
.........\..\bpsk_fpga.sim.vwf
.........\..\bpsk_fpga.sld_design_entry.sci
.........\..\bpsk_fpga.sld_design_entry_dsc.sci
.........\..\bpsk_fpga.syn_hier_info
.........\..\bpsk_fpga.tan.qmsg
.........\..\bpsk_fpga_cmp.qrpt
.........\..\bpsk_fpga_sim.qrpt
.........\bpsk_fpga.bdf
.........\bpsk_fpga.bsf
.........\bpsk_fpga.cdf
.........\bpsk_fpga.done
.........\bpsk_fpga.dpf
.........\bpsk_fpga.fit.eqn
.........\bpsk_fpga.fit.rpt
.........\bpsk_fpga.fit.smsg
.........\bpsk_fpga.fit.summary
.........\bpsk_fpga.flow.rpt
.........\bpsk_fpga.map.eqn
.........\bpsk_fpga.map.rpt
.........\bpsk_fpga.map.summary
.........\bpsk_fpga.pin
.........\bpsk_fpga.pof
.........\bpsk_fpga.qpf
.........\bpsk_fpga.qsf
.........\bpsk_fpga.qws
.........\bpsk_fpga.sim.rpt
.........\bpsk_fpga.sof
.........\bpsk_fpga.tan.rpt
.........\bpsk_fpga.tan.summary
.........\bpsk_fpga_assignment_defaults.qdf
.........\cmp_state.ini
.........\Decision.bsf
.........\DelayOyx.bsf
.........\fenpin.bsf
.........\PLL_CLK.bsf
.........\PLL_CLK.cmp
.........\PLL_CLK.ppf
.........\PLL_CLK.vhd
.........\PLL_CLK_wave0.jpg
.........\PLL_CLK_waveforms.html
.........\pulse.bsf
.........\RemoveBurr.bsf
.........\stable.bsf
.........\wave\bpsk_fpga.vwf
.........\....\Decision.vwf
.........\....\fenpin.vwf
.........\....\fm_decode.vwf
.........\....\pulse.vwf
.........\....\removeburr.vwf
.........\....\signalsyn.vwf
.........\....\stable.vwf
.........\source\Decision.vhd
.........\......\DelayOyx.vhd
.........\......\div_clk.vhd
.........\......\fenpin.vhd
.........\......\FM_Decode.vhd
.........\......\oyxtemp.bdf
.........\......\pulse.vhd
.........\......\RemoveBurr.vhd
.........\......\SignalSyn.bdf
.........\......\SignSyn_book.bdf
.........\......\SignSyn_book.bsf
.........\......\stable.vhd
.........\db\add_sub_n2i.tdf
.........\..\bpsk_fpga.analyze_file.qmsg
.........\..\bpsk_fpga.asm.qmsg
.........\..\bpsk_fpga.asm_labs.ddb
.........\..\bpsk_fpga.cbx.xml
.........\..\bpsk_fpga.cmp.cdb
.........\..\bpsk_fpga.cmp.hdb
.........\..\bpsk_fpga.cmp.kpt
.........\..\bpsk_fpga.cmp.logdb
.........\..\bpsk_fpga.cmp.rdb
.........\..\bpsk_fpga.cmp.tdb
.........\..\bpsk_fpga.cmp0.ddb
.........\..\bpsk_fpga.cmp2.ddb
.........\..\bpsk_fpga.dbp
.........\..\bpsk_fpga.db_info
.........\..\bpsk_fpga.eco.cdb
.........\..\bpsk_fpga.eds_overflow
.........\..\bpsk_fpga.fit.qmsg
.........\..\bpsk_fpga.hier_info
.........\..\bpsk_fpga.hif
.........\..\bpsk_fpga.map.cdb
.........\..\bpsk_fpga.map.hdb
.........\..\bpsk_fpga.map.logdb
.........\..\bpsk_fpga.map.qmsg
.........\..\bpsk_fpga.pre_map.cdb
.........\..\bpsk_fpga.pre_map.hdb
.........\..\bpsk_fpga.psp
.........\..\bpsk_fpga.rtlv.hdb
.........\..\bpsk_fpga.rtlv_sg.cdb
.........\..\bpsk_fpga.rtlv_sg_swap.cdb
.........\..\bpsk_fpga.sgdiff.cdb
.........\..\bpsk_fpga.sgdiff.hdb
.........\..\bpsk_fpga.signalprobe.cdb
.........\..\bpsk_fpga.sim.hdb
.........\..\bpsk_fpga.sim.qmsg
.........\..\bpsk_fpga.sim.rdb
.........\..\bpsk_fpga.sim.vwf
.........\..\bpsk_fpga.sld_design_entry.sci
.........\..\bpsk_fpga.sld_design_entry_dsc.sci
.........\..\bpsk_fpga.syn_hier_info
.........\..\bpsk_fpga.tan.qmsg
.........\..\bpsk_fpga_cmp.qrpt
.........\..\bpsk_fpga_sim.qrpt