文件名称:processor
介绍说明－－下载内容均来自于网络，请自行研究使用
文件中包含一个简单MIIPS CPU的Verilog源代码-File contains a simple MIIPS CPU in Verilog source code
(系统自动生成,下载前可以参看下载内容)
下载文件列表
processor\mips.v
.........\mux3.v.bak
.........\mux3.v
.........\memfile.dat
.........\sl2.v
.........\regfile.v
.........\signext.v
.........\hazardunit.v
.........\datapath.v.bak
.........\datapath.v
.........\testbench.v.bak
.........\testbench.v
.........\processor.cr.mti
.........\memfile.dat.bak
.........\processor.mpf
.........\transcript
.........\datapath1.v
.........\hewenjuan.mpf
.........\test_flop.v
.........\flop.v
.........\equal.v
.........\flopr.v
.........\top.v
.........\adder.v
.........\mux2.v
.........\controller.v
.........\dmem.v
.........\vsim.wlf
.........\alu.v
.........\imem.v
.........\hewenjuan.cr.mti
.........\top.v.bak
.........\flopr1.v
.........\flopr3.v
.........\flopr4.v
.........\flop2.v
.........\controller.v.bak
.........\mips.v.bak
.........\work\_info
.........\....\memfile.dat
.........\....\flopr11\_primary.vhd
.........\....\.......\verilog.asm
.........\....\.......\_primary.dat
.........\....\flopr11
.........\....\mux4\_primary.vhd
.........\....\....\verilog.asm
.........\....\....\_primary.dat
.........\....\mux4
.........\....\hazardunit\_primary.vhd
.........\....\..........\verilog.asm
.........\....\..........\_primary.dat
.........\....\hazardunit
.........\....\regfile\_primary.vhd
.........\....\.......\verilog.asm
.........\....\.......\_primary.dat
.........\....\regfile
.........\....\signext\_primary.vhd
.........\....\.......\verilog.asm
.........\....\.......\_primary.dat
.........\....\signext
.........\....\.l2\_primary.vhd
.........\....\...\verilog.asm
.........\....\...\_primary.dat
.........\....\sl2
.........\....\flopr4\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\flopr4
.........\....\.....3\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\flopr3
.........\....\.....2\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\flopr2
.........\....\.....1\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\flopr1
.........\....\aludec\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\aludec
.........\....\maindec\_primary.vhd
.........\....\.......\verilog.asm
.........\....\.......\_primary.dat
.........\....\maindec
.........\....\controller\_primary.vhd
.........\....\..........\verilog.asm
.........\....\..........\_primary.dat
.........\....\controller
.........\....\datapath\_primary.vhd
.........\....\........\verilog.asm
.........\....\........\_primary.dat
.........\....\datapath
.........\....\flopr\_primary.vhd
.........\....\.....\verilog.asm
.........\....\.....\_primary.dat
.........\....\flopr
.........\mux3.v.bak
.........\mux3.v
.........\memfile.dat
.........\sl2.v
.........\regfile.v
.........\signext.v
.........\hazardunit.v
.........\datapath.v.bak
.........\datapath.v
.........\testbench.v.bak
.........\testbench.v
.........\processor.cr.mti
.........\memfile.dat.bak
.........\processor.mpf
.........\transcript
.........\datapath1.v
.........\hewenjuan.mpf
.........\test_flop.v
.........\flop.v
.........\equal.v
.........\flopr.v
.........\top.v
.........\adder.v
.........\mux2.v
.........\controller.v
.........\dmem.v
.........\vsim.wlf
.........\alu.v
.........\imem.v
.........\hewenjuan.cr.mti
.........\top.v.bak
.........\flopr1.v
.........\flopr3.v
.........\flopr4.v
.........\flop2.v
.........\controller.v.bak
.........\mips.v.bak
.........\work\_info
.........\....\memfile.dat
.........\....\flopr11\_primary.vhd
.........\....\.......\verilog.asm
.........\....\.......\_primary.dat
.........\....\flopr11
.........\....\mux4\_primary.vhd
.........\....\....\verilog.asm
.........\....\....\_primary.dat
.........\....\mux4
.........\....\hazardunit\_primary.vhd
.........\....\..........\verilog.asm
.........\....\..........\_primary.dat
.........\....\hazardunit
.........\....\regfile\_primary.vhd
.........\....\.......\verilog.asm
.........\....\.......\_primary.dat
.........\....\regfile
.........\....\signext\_primary.vhd
.........\....\.......\verilog.asm
.........\....\.......\_primary.dat
.........\....\signext
.........\....\.l2\_primary.vhd
.........\....\...\verilog.asm
.........\....\...\_primary.dat
.........\....\sl2
.........\....\flopr4\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\flopr4
.........\....\.....3\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\flopr3
.........\....\.....2\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\flopr2
.........\....\.....1\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\flopr1
.........\....\aludec\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\aludec
.........\....\maindec\_primary.vhd
.........\....\.......\verilog.asm
.........\....\.......\_primary.dat
.........\....\maindec
.........\....\controller\_primary.vhd
.........\....\..........\verilog.asm
.........\....\..........\_primary.dat
.........\....\controller
.........\....\datapath\_primary.vhd
.........\....\........\verilog.asm
.........\....\........\_primary.dat
.........\....\datapath
.........\....\flopr\_primary.vhd
.........\....\.....\verilog.asm
.........\....\.....\_primary.dat
.........\....\flopr