文件名称:VHDL-djdplj
介绍说明－－下载内容均来自于网络，请自行研究使用
基于VHDL语言的十进制等精度频率计的设计，采用VHDL语言，运用自顶向下的设计思想，
将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。-VHDL language based on the decimal precision frequency meter, etc. The design, using VHDL language, the use of top-down design, the system is divided by function layer hierarchical design method, the use of Quartus8.0 development environment, to achieve a frequency meter design.
将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。-VHDL language based on the decimal precision frequency meter, etc. The design, using VHDL language, the use of top-down design, the system is divided by function layer hierarchical design method, the use of Quartus8.0 development environment, to achieve a frequency meter design.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VHDL-djdplj.pdf