文件名称:mod6asynchro
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this is a code for mod-6 asynchronous counter in verilog.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
mod6asynchro\automake.log
............\mod6asynchro.dhp
............\mod6asynchro.ise
............\mod6asynchro.ise_ISE_Backup
............\mod6asynchro.ldo
............\mod6asynchro.lso
............\mod6asynchro.prj
............\mod6asynchro.stx
............\mod6asynchro.v
............\mod6asynchro_vhdl.prj
............\prjname.lso
............\Project.dhp
............\transcript
............\vsim.wlf
............\wave.do
............\.ork\dff\verilog.psm
............\....\...\_primary.dat
............\....\...\_primary.vhd
............\....\glbl\verilog.psm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\jkff\verilog.psm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\mod6asynchro\verilog.psm
............\....\............\_primary.dat
............\....\............\_primary.vhd
............\....\_info
............\xst\work\hdllib.ref
............\...\....\vlg19\jkff.bin
............\...\....\...28\dff.bin
............\...\....\...55\mod6asynchro.bin
............\__projnav\mod6asynchro.gfl
............\.........\mod6asynchro.xst
............\.........\mod6asynchro_flowplus.gfl
............\.........\xst_sprjTOstx_tcl.rsp
............\__projnav.log
............\xst\work\vlg19
............\...\....\vlg28
............\...\....\vlg55
............\work\dff
............\....\glbl
............\....\jkff
............\....\mod6asynchro
............\xst\work
............\work
............\xst
............\_xmsgs
............\__projnav
mod6asynchro
............\mod6asynchro.dhp
............\mod6asynchro.ise
............\mod6asynchro.ise_ISE_Backup
............\mod6asynchro.ldo
............\mod6asynchro.lso
............\mod6asynchro.prj
............\mod6asynchro.stx
............\mod6asynchro.v
............\mod6asynchro_vhdl.prj
............\prjname.lso
............\Project.dhp
............\transcript
............\vsim.wlf
............\wave.do
............\.ork\dff\verilog.psm
............\....\...\_primary.dat
............\....\...\_primary.vhd
............\....\glbl\verilog.psm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\jkff\verilog.psm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\mod6asynchro\verilog.psm
............\....\............\_primary.dat
............\....\............\_primary.vhd
............\....\_info
............\xst\work\hdllib.ref
............\...\....\vlg19\jkff.bin
............\...\....\...28\dff.bin
............\...\....\...55\mod6asynchro.bin
............\__projnav\mod6asynchro.gfl
............\.........\mod6asynchro.xst
............\.........\mod6asynchro_flowplus.gfl
............\.........\xst_sprjTOstx_tcl.rsp
............\__projnav.log
............\xst\work\vlg19
............\...\....\vlg28
............\...\....\vlg55
............\work\dff
............\....\glbl
............\....\jkff
............\....\mod6asynchro
............\xst\work
............\work
............\xst
............\_xmsgs
............\__projnav
mod6asynchro