文件名称:mem64_to_pcitarget_verilog
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This design example shows possible interface between instantiation of Altera s 64-bit pci target megafunction and 64-bit synchronous memory -This design example shows possible interface between instantiation of Altera s 64-bit pci target megafunction and 64-bit synchronous memory
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下载文件列表
mem64_to_pcitarget_verilog\mem256x32.v
..........................\pt64.v
..........................\pt64.vo
..........................\readme.txt
..........................\targ_mem64.v
..........................\top_t64.v
mem64_to_pcitarget_verilog
..........................\pt64.v
..........................\pt64.vo
..........................\readme.txt
..........................\targ_mem64.v
..........................\top_t64.v
mem64_to_pcitarget_verilog