文件名称:spdmeasure
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 22.84mb
- 下载次数：
- 0次
- 提 供 者：
- dingw*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
脉冲测速，用VERILOG语言实现，自动跳档-Pulse velocity, with the VERILOG language, automatically skip files
(系统自动生成,下载前可以参看下载内容)
下载文件列表
sac\component\work\aa\aa.cxf
...\.........\....\..\aa.sdb
...\.........\....\iobuf\iobuf.cxf
...\.........\....\.....\iobuf.sdb
...\.........\....\IO_BUF\IO_BUF.cxf
...\.........\....\......\IO_BUF.sdb
...\.........\....\sac\sac.cxf
...\.........\....\...\sac.sdb
...\..nstraint\data\sac_con.pdc.ce
...\..........\....\sac_con.pdc.lce
...\..........\sac_con.pdc
...\cpu_main.v
...\designer\impl1\ada01332-1.tmp
...\........\.....\af0.ini
...\........\.....\ccc.ide_des
...\........\.....\designer.log
...\........\.....\designer_synth_check.log
...\........\.....\freaquency_measure.ide_des
...\........\.....\iobuf.ide_des
...\........\.....\IO_BUF.ide_des
...\........\.....\newCore.ide_des
...\........\.....\phase_measure.ide_des
...\........\.....\PLL2.ide_des
...\........\.....\PLLMUL2.ide_des
...\........\.....\pluse_count.ide_des
...\........\.....\sac_top.adb
...\........\.....\........dtf\verify.log
...\........\.....\sac_top.ide_des
...\........\.....\sac_top.lok
...\........\.....\sac_top.pdb
...\........\.....\sac_top.pdb.depends
...\........\.....\sac_top.stp
...\........\.....\sac_top.tcl
...\........\.....\sac_top_ba.sdf
...\........\.....\sac_top_ba.v
...\........\.....\........fp\$$FlashPro_08456.L$$
...\........\.....\..........\projectData\sac_top.stp
...\........\.....\..........\sac_top.log
...\........\.....\..........\sac_top.pro
...\........\....2\designer.log
...\........\.....\freaquency_measure.ide_des
...\........\.....\iobuf.ide_des
...\........\.....\IO_BUF.ide_des
...\........\.....\newCore.ide_des
...\........\.....\phase_measure.ide_des
...\........\.....\pluse_count.ide_des
...\........\.....\sac_top.adb
...\........\.....\........dtf\verify.log
...\........\.....\sac_top.ide_des
...\........\.....\sac_top.pdb
...\........\.....\sac_top.pdb.depends
...\........\.....\sac_top.stp
...\........\.....\sac_top.tcl
...\........\sac_top.stp
...\hdl\freaquency_measure.v
...\...\phase_measure.v
...\...\pluse_count.v
...\...\sac_top.v
...\...\waveperl.log
...\hdl.rar
...\pluse_count.v
...\sac.prj
...\.imulation\modelsim.ini
...\..........\modelsim.ini.sav
...\..........\modelsim.log
...\..........\presynth\@i@o@b@u@f\verilog.psm
...\..........\........\..........\_primary.dat
...\..........\........\..........\_primary.dbs
...\..........\........\..........\_primary.vhd
...\..........\........\.p@l@l@m@u@l2\verilog.psm
...\..........\........\.............\_primary.dat
...\..........\........\.............\_primary.dbs
...\..........\........\.............\_primary.vhd
...\..........\........\phase_measure\verilog.psm
...\..........\........\.............\_primary.dat
...\..........\........\.............\_primary.dbs
...\..........\........\.............\_primary.vhd
...\..........\........\_info
...\..........\........\.temp\vlog29nxnm
...\..........\........\.....\vlog2shx6q
...\..........\........\.....\vlog9e45z8
...\..........\........\.....\vlogdzxibe
...\..........\........\_vmake
...\..........\run.do
...\.martgen\ccc\ccc.cxf
...\........\...\ccc.gen
...\........\...\ccc.log
...\........\...\ccc.v
...\........\IOBUF\IOBUF.cxf
...\........\.....\IOBUF.gen
...\........\.....\IOBUF.log
...\........\.....\IOBUF.v
...\........\IOBUF_work.ixf
...\........\PLL2\PLL2.cxf
...\........\....\PLL2.gen
...\........\....\PLL2.log
...\........\....\PLL2.v
...\........\PLL2_work.ixf
...\........\...MUL2\PLLMUL2.cxf
...\........\.......\PLLMUL2.gen
...\.........\....\..\aa.sdb
...\.........\....\iobuf\iobuf.cxf
...\.........\....\.....\iobuf.sdb
...\.........\....\IO_BUF\IO_BUF.cxf
...\.........\....\......\IO_BUF.sdb
...\.........\....\sac\sac.cxf
...\.........\....\...\sac.sdb
...\..nstraint\data\sac_con.pdc.ce
...\..........\....\sac_con.pdc.lce
...\..........\sac_con.pdc
...\cpu_main.v
...\designer\impl1\ada01332-1.tmp
...\........\.....\af0.ini
...\........\.....\ccc.ide_des
...\........\.....\designer.log
...\........\.....\designer_synth_check.log
...\........\.....\freaquency_measure.ide_des
...\........\.....\iobuf.ide_des
...\........\.....\IO_BUF.ide_des
...\........\.....\newCore.ide_des
...\........\.....\phase_measure.ide_des
...\........\.....\PLL2.ide_des
...\........\.....\PLLMUL2.ide_des
...\........\.....\pluse_count.ide_des
...\........\.....\sac_top.adb
...\........\.....\........dtf\verify.log
...\........\.....\sac_top.ide_des
...\........\.....\sac_top.lok
...\........\.....\sac_top.pdb
...\........\.....\sac_top.pdb.depends
...\........\.....\sac_top.stp
...\........\.....\sac_top.tcl
...\........\.....\sac_top_ba.sdf
...\........\.....\sac_top_ba.v
...\........\.....\........fp\$$FlashPro_08456.L$$
...\........\.....\..........\projectData\sac_top.stp
...\........\.....\..........\sac_top.log
...\........\.....\..........\sac_top.pro
...\........\....2\designer.log
...\........\.....\freaquency_measure.ide_des
...\........\.....\iobuf.ide_des
...\........\.....\IO_BUF.ide_des
...\........\.....\newCore.ide_des
...\........\.....\phase_measure.ide_des
...\........\.....\pluse_count.ide_des
...\........\.....\sac_top.adb
...\........\.....\........dtf\verify.log
...\........\.....\sac_top.ide_des
...\........\.....\sac_top.pdb
...\........\.....\sac_top.pdb.depends
...\........\.....\sac_top.stp
...\........\.....\sac_top.tcl
...\........\sac_top.stp
...\hdl\freaquency_measure.v
...\...\phase_measure.v
...\...\pluse_count.v
...\...\sac_top.v
...\...\waveperl.log
...\hdl.rar
...\pluse_count.v
...\sac.prj
...\.imulation\modelsim.ini
...\..........\modelsim.ini.sav
...\..........\modelsim.log
...\..........\presynth\@i@o@b@u@f\verilog.psm
...\..........\........\..........\_primary.dat
...\..........\........\..........\_primary.dbs
...\..........\........\..........\_primary.vhd
...\..........\........\.p@l@l@m@u@l2\verilog.psm
...\..........\........\.............\_primary.dat
...\..........\........\.............\_primary.dbs
...\..........\........\.............\_primary.vhd
...\..........\........\phase_measure\verilog.psm
...\..........\........\.............\_primary.dat
...\..........\........\.............\_primary.dbs
...\..........\........\.............\_primary.vhd
...\..........\........\_info
...\..........\........\.temp\vlog29nxnm
...\..........\........\.....\vlog2shx6q
...\..........\........\.....\vlog9e45z8
...\..........\........\.....\vlogdzxibe
...\..........\........\_vmake
...\..........\run.do
...\.martgen\ccc\ccc.cxf
...\........\...\ccc.gen
...\........\...\ccc.log
...\........\...\ccc.v
...\........\IOBUF\IOBUF.cxf
...\........\.....\IOBUF.gen
...\........\.....\IOBUF.log
...\........\.....\IOBUF.v
...\........\IOBUF_work.ixf
...\........\PLL2\PLL2.cxf
...\........\....\PLL2.gen
...\........\....\PLL2.log
...\........\....\PLL2.v
...\........\PLL2_work.ixf
...\........\...MUL2\PLLMUL2.cxf
...\........\.......\PLLMUL2.gen