文件名称:e1_vhdl
介绍说明－－下载内容均来自于网络，请自行研究使用
用VHDL在FPGA内部实现E1的接口，适合通讯相关专业硬件开发使用-Within the FPGA implementation using VHDL E1 interface, the hardware for communications-related professional development to use
(系统自动生成,下载前可以参看下载内容)
下载文件列表
e1_vhdl\e1_framer\clkdiv_8.vhd
.......\.........\crc_4.vhd
.......\.........\crc_insert.vhd
.......\.........\e1_buffer.vhd
.......\.........\e1_buffer1.vhd
.......\.........\e1_crc.vhd
.......\.........\e1_deframer.vhd
.......\.........\e1_defrm.vhd
.......\.........\e1_fas.vhd
.......\.........\e1_fasdecode.vhd
.......\.........\e1_frm.vhd
.......\.........\e1_package.vhd
.......\.........\fas_insert.vhd
.......\.........\fas_sync.vhd
.......\.........\fas_sync2.vhd
.......\.........\ram_ex.vhd
.......\.........\test_e1.vhd
.......\.........\test_fas_insert.vhd
.......\.........\up_interface.vhd
.......\.........\up_interface1.vhd
.......\fas_insert.vhd
.......\e1_framer
e1_vhdl
.......\.........\crc_4.vhd
.......\.........\crc_insert.vhd
.......\.........\e1_buffer.vhd
.......\.........\e1_buffer1.vhd
.......\.........\e1_crc.vhd
.......\.........\e1_deframer.vhd
.......\.........\e1_defrm.vhd
.......\.........\e1_fas.vhd
.......\.........\e1_fasdecode.vhd
.......\.........\e1_frm.vhd
.......\.........\e1_package.vhd
.......\.........\fas_insert.vhd
.......\.........\fas_sync.vhd
.......\.........\fas_sync2.vhd
.......\.........\ram_ex.vhd
.......\.........\test_e1.vhd
.......\.........\test_fas_insert.vhd
.......\.........\up_interface.vhd
.......\.........\up_interface1.vhd
.......\fas_insert.vhd
.......\e1_framer
e1_vhdl