文件名称:I2C

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 2.21mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 张**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

基于FPGA实现的I2C接口设计,完整的代码,而且有完整的测试代码哦,可用ISE直接打开-FPGA-based implementation of the I2C interface design, complete code, and a complete test code, ISE can directly open,
相关搜索: I2c

(系统自动生成,下载前可以参看下载内容)

下载文件列表

I2C\automake.log

...\coregen.log

...\coregen.prj

...\I2C.dhp

...\i2c_master_bit_ctrl.cmd_log

...\i2c_master_bit_ctrl.lso

...\i2c_master_bit_ctrl.ngc

...\i2c_master_bit_ctrl.ngr

...\i2c_master_bit_ctrl.prj

...\i2c_master_bit_ctrl.stx

...\i2c_master_bit_ctrl.syr

...\i2c_master_bit_ctrl.v

...\i2c_master_bit_ctrl.v.bak

...\i2c_master_bit_ctrl_vhdl.prj

...\i2c_master_byte_ctrl.cmd_log

...\i2c_master_byte_ctrl.lso

...\i2c_master_byte_ctrl.ngc

...\i2c_master_byte_ctrl.ngr

...\i2c_master_byte_ctrl.prj

...\i2c_master_byte_ctrl.stx

...\i2c_master_byte_ctrl.syr

...\i2c_master_byte_ctrl.v

...\i2c_master_byte_ctrl.v.bak

...\i2c_master_byte_ctrl_vhdl.prj

...\i2c_master_defines.v

...\i2c_master_defines.v.bak

...\i2c_master_top.cmd_log

...\i2c_master_top.lso

...\i2c_master_top.ngc

...\i2c_master_top.ngr

...\i2c_master_top.prj

...\i2c_master_top.stx

...\i2c_master_top.syr

...\i2c_master_top.v

...\i2c_master_top.v.bak

...\i2c_master_top_vhdl.prj

...\i2c_slave_model.fdo

...\i2c_slave_model.ndo

...\i2c_slave_model.udo

...\i2c_slave_model.v

...\i2c_slave_model.v.bak

...\prjname.lso

...\timescale.v

...\transcript

...\tst_bench_top.v

...\wb_master_model.v

...\wb_master_model.v.bak

...\__projnav.log

...\work\_info

...\....\i2c_slave_model\verilog.asm

...\....\...............\_primary.dat

...\....\...............\_primary.vhd

...\....\glbl\verilog.asm

...\....\....\_primary.dat

...\....\....\_primary.vhd

...\....\i2c_master_bit_ctrl\_primary.vhd

...\....\...................\verilog.asm

...\....\...................\_primary.dat

...\....\............yte_ctrl\_primary.vhd

...\....\....................\verilog.asm

...\....\....................\_primary.dat

...\....\wb_master_model\_primary.vhd

...\....\...............\verilog.asm

...\....\...............\_primary.dat

...\....\i2c_master_top\_primary.vhd

...\....\..............\verilog.asm

...\....\..............\_primary.dat

...\....\tst_bench_top\_primary.vhd

...\....\.............\verilog.asm

...\....\.............\_primary.dat

...\I2C_xdb\tmp\npl\version

...\.......\...\ise\__OBJSTORE__\PnAutoRun\Scripts\RunOnce_tcl

...\.......\...\...\............\.........\.......\RunOnce_tcl_StrTbl

...\.......\...\...\............\.rojectNavigatorGui\GuiProjectData

...\.......\...\...\............\...................\GuiProjectData_StrTbl

...\.......\...\...\............\xreport\Gc_RvReportViewer-Current-Module

...\.......\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl

...\.......\...\...\............\.......\Gc_RvReportViewer-Module-Data-i2c_master_byte_ctrl

...\.......\...\...\............\.......\Gc_RvReportViewer-Module-Data-i2c_master_byte_ctrl_StrTbl

...\.......\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default

...\.......\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl

...\.......\...\...\............\ISimPlugin\SignalOrdering1\tst_bench_top_isim_beh.exe

...\.......\...\...\............\..........\...............\tst_bench_top_isim_beh.exe_StrTbl

...\.......\...\...\............\ProjectNavigator\dpm_project_main\dpm_project_main

...\.......\...\...\............\................\................\dpm_project_main_StrTbl

...\.......\...\...\............\................\................\NameMap

...\.......\...\...\............\................\................\NameMap_StrTbl

...\.......\...\...\............\................\__stored_objects__

...\.......\...\...\............\................\__stored_objects___StrTbl

...\.......\...\...\............\................\__stored_object_table__

...\.......\...\...\............\HierarchicalDesign\HDProject\HDProject

...\.......\...\...\............\..................\.........\HDProject_StrTbl

...\.......\...\...\..REGISTRY__\Autonym\regkeys

...\.......\...\...\............\HierarchicalDesign\HDProject\regkeys

...\.......\...\...\............\..................\regkeys

...\.......\...\...\............\ProjectNavigator\regkeys

...\.......\...\...\............\................Gui\regkeys

...\.......\...\...\............\SrcCtrl\regkeys

...\.......\...\...\............\XSLTProcess\regkey

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 本站是交换下载平台,提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度更多...
  • 请直接用浏览器下载本站内容,不要使用迅雷之类的下载软件,用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.

相关评论

暂无评论内容.

发表评论

*主  题:
*内  容:
*验 证 码:

源码中国 www.ymcn.org