文件名称:miniuart2

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 2.47mb
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  • 0次
  • 提 供 者:
  • 李*
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介绍说明--下载内容均来自于网络,请自行研究使用

用VHDL在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an

interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core.

It works fine connected to the serial port of a PC for data exchange with custom

electronic.

It was built in the perspective to be very small, but efficient. It had to fit in a small FPGA.

It is not suited to interface a modem as there is no control handshaking (CTS/RTS).

It integrate two separate clocks, one for wishbone bus, the other for bitstream generation.

This has the advantage to let the user bring his own desired frequency for the baudrate.
相关搜索: miniuart2
cpld
RS-232
pc

(系统自动生成,下载前可以参看下载内容)

下载文件列表

miniuart2\branches\avendor\doc\MiniUart.pdf

.........\........\.......\...\src\MiniUART.doc

.........\........\.......\impl\info.txt

.........\........\.......\....\Xilinx_xc2s15\automake.log

.........\........\.......\....\.............\miniuart.jhd

.........\........\.......\....\.............\par.opt

.........\........\.......\....\.............\Rxunit.jhd

.........\........\.......\....\.............\Txunit.jhd

.........\........\.......\....\.............\uart.bld

.........\........\.......\....\.............\uart.cup

.........\........\.......\....\.............\uart.dly

.........\........\.......\....\.............\uart.mrp

.........\........\.......\....\.............\uart.nc1

.........\........\.......\....\.............\uart.ncd

.........\........\.......\....\.............\uart.ngc

.........\........\.......\....\.............\uart.ngd

.........\........\.......\....\.............\uart.ngm

.........\........\.......\....\.............\uart.pad

.........\........\.......\....\.............\uart.par

.........\........\.......\....\.............\uart.pcf

.........\........\.......\....\.............\uart.prj

.........\........\.......\....\.............\uart.syr

.........\........\.......\....\.............\uart.xpi

.........\........\.......\....\.............\uart.xst

.........\........\.......\....\.............\uart._prj

.........\........\.......\....\.............\uart_map.ncd

.........\........\.......\....\.............\uart_ngdbuild.nav

.........\........\.......\....\.............\utils.jhd

.........\........\.......\....\.............\xilinx.jid

.........\........\.......\....\.............\Xilinx.npl

.........\........\.......\....\.............\_map.log

.........\........\.......\....\.............\_map.rsp

.........\........\.......\....\.............\_nc1TOncd_exewrap.rsp

.........\........\.......\....\.............\_ngdTOnc1_exewrap.rsp

.........\........\.......\....\.............\...o\netlist.lst

.........\........\.......\....\.............\_par.log

.........\........\.......\....\.............\_par.rsp

.........\........\.......\....\.............\_prepar.rsp

.........\........\.......\....\.............\__ednTOngd_exewrap.rsp

.........\........\.......\....\.............\__launchTA.tcl

.........\........\.......\....\.............\__ngdbuild.rsp

.........\........\.......\....\.............\__projnav.log

.........\........\.......\....\.............\__uart_2prj_exewrap.rsp

.........\........\.......\....\.........s10\Xilinx\express.ini

.........\........\.......\....\............\......\lib\XILINX.BLK

.........\........\.......\....\............\......\...\XILINX.DIR

.........\........\.......\....\............\......\...\XILINX.FIG

.........\........\.......\....\............\......\...\XILINX.FLG

.........\........\.......\....\............\......\...\XILINX.GNR

.........\........\.......\....\............\......\...\XILINX.HDR

.........\........\.......\....\............\......\...\XILINX.ID

.........\........\.......\....\............\......\...\XILINX.INI

.........\........\.......\....\............\......\...\XILINX.MAP

.........\........\.......\....\............\......\...\XILINX.MOD

.........\........\.......\....\............\......\...\XILINX.PIN

.........\........\.......\....\............\......\...\XILINX.SYM

.........\........\.......\....\............\......\...\XILINX.SYN

.........\........\.......\....\............\......\...\XILINX.VIS

.........\........\.......\....\............\......\miniuart.log

.........\........\.......\....\............\......\miniuart.vhd

.........\........\.......\....\............\......\rxunit.log

.........\........\.......\....\............\......\Rxunit.vhd

.........\........\.......\....\............\......\txunit.log

.........\........\.......\....\............\......\Txunit.vhd

.........\........\.......\....\............\......\utils.log

.........\........\.......\....\............\......\utils.vhd

.........\........\.......\....\............\......\xilinx\chips\ver1\ver1.cst

.........\........\.......\....\............\......\......\.....

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