文件名称:traffic_lights
介绍说明－－下载内容均来自于网络，请自行研究使用
使用VHDL编写的交通灯程序，主要分为分频模块、控制模块、显示模块-Use the traffic lights procedures, write VHDL mainly divided into frequency module, control module, display module
(系统自动生成,下载前可以参看下载内容)
下载文件列表
traffic_lights\clk_gen.vhd
..............\clk_gen.qpf
..............\clk_gen.qsf
..............\db\clk_gen.db_info
..............\..\clk_gen.cbx.xml
..............\..\clk_gen.hif
..............\..\clk_gen.hier_info
..............\..\clk_gen.psp
..............\..\clk_gen.pss
..............\..\clk_gen.dbp
..............\..\clk_gen.syn_hier_info
..............\..\clk_gen.map.qmsg
..............\..\clk_gen.rtlv_sg.cdb
..............\..\clk_gen.rtlv.hdb
..............\..\clk_gen.rtlv_sg_swap.cdb
..............\..\clk_gen.pre_map.hdb
..............\..\clk_gen.pre_map.cdb
..............\..\clk_gen.map.logdb
..............\..\clk_gen.sgdiff.cdb
..............\..\clk_gen.sgdiff.hdb
..............\..\clk_gen.sld_design_entry_dsc.sci
..............\..\clk_gen.map.cdb
..............\..\clk_gen.map.hdb
..............\..\clk_gen.fit.qmsg
..............\..\clk_gen.cmp.logdb
..............\..\clk_gen.asm.qmsg
..............\..\clk_gen.asm_labs.ddb
..............\..\clk_gen.tan.qmsg
..............\..\clk_gen.cmp.tdb
..............\..\clk_gen.cmp0.ddb
..............\..\clk_gen.cmp.cdb
..............\..\clk_gen.signalprobe.cdb
..............\..\clk_gen.cmp.hdb
..............\..\clk_gen.cmp.rdb
..............\..\clk_gen.sld_design_entry.sci
..............\..\clk_gen.eco.cdb
..............\clk_gen.map.rpt
..............\clk_gen.flow.rpt
..............\clk_gen.map.summary
..............\clk_gen.pin
..............\clk_gen.fit.rpt
..............\clk_gen.fit.smsg
..............\clk_gen.fit.summary
..............\clk_gen.pof
..............\clk_gen.asm.rpt
..............\clk_gen.tan.summary
..............\clk_gen.tan.rpt
..............\clk_gen.done
..............\clk_gen.dpf
..............\control.vhd
..............\selec.vhd
..............\clk_gen.qws
..............\db
traffic_lights
..............\clk_gen.qpf
..............\clk_gen.qsf
..............\db\clk_gen.db_info
..............\..\clk_gen.cbx.xml
..............\..\clk_gen.hif
..............\..\clk_gen.hier_info
..............\..\clk_gen.psp
..............\..\clk_gen.pss
..............\..\clk_gen.dbp
..............\..\clk_gen.syn_hier_info
..............\..\clk_gen.map.qmsg
..............\..\clk_gen.rtlv_sg.cdb
..............\..\clk_gen.rtlv.hdb
..............\..\clk_gen.rtlv_sg_swap.cdb
..............\..\clk_gen.pre_map.hdb
..............\..\clk_gen.pre_map.cdb
..............\..\clk_gen.map.logdb
..............\..\clk_gen.sgdiff.cdb
..............\..\clk_gen.sgdiff.hdb
..............\..\clk_gen.sld_design_entry_dsc.sci
..............\..\clk_gen.map.cdb
..............\..\clk_gen.map.hdb
..............\..\clk_gen.fit.qmsg
..............\..\clk_gen.cmp.logdb
..............\..\clk_gen.asm.qmsg
..............\..\clk_gen.asm_labs.ddb
..............\..\clk_gen.tan.qmsg
..............\..\clk_gen.cmp.tdb
..............\..\clk_gen.cmp0.ddb
..............\..\clk_gen.cmp.cdb
..............\..\clk_gen.signalprobe.cdb
..............\..\clk_gen.cmp.hdb
..............\..\clk_gen.cmp.rdb
..............\..\clk_gen.sld_design_entry.sci
..............\..\clk_gen.eco.cdb
..............\clk_gen.map.rpt
..............\clk_gen.flow.rpt
..............\clk_gen.map.summary
..............\clk_gen.pin
..............\clk_gen.fit.rpt
..............\clk_gen.fit.smsg
..............\clk_gen.fit.summary
..............\clk_gen.pof
..............\clk_gen.asm.rpt
..............\clk_gen.tan.summary
..............\clk_gen.tan.rpt
..............\clk_gen.done
..............\clk_gen.dpf
..............\control.vhd
..............\selec.vhd
..............\clk_gen.qws
..............\db
traffic_lights