文件名称:DDFS_verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
直接数字频率综合器，采用ROM压缩法，经过FPGA验证和AISC实现-Direct digital frequency synthesizer, using ROM compression method, validation and AISC through FPGA Implementation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DDFS_verilog\DDFS.v
............\freq_adder.v
............\freq_random.v
............\phase_cos.txt
............\phase_sin.txt
............\phas_gene.v
............\tb_ddfs.v
DDFS_verilog
............\freq_adder.v
............\freq_random.v
............\phase_cos.txt
............\phase_sin.txt
............\phas_gene.v
............\tb_ddfs.v
DDFS_verilog