hdl\addSub.v

...\Alu.v

...\Alu.v.bak

...\bitScanFwd.v

...\bitScanRev.v

...\bitScanRev64.v

...\Check4Exception.v

...\Check4Nans.v

...\chkOps.v

...\chkOps.v.bak

...\chkResult.v

...\chkResult.v.bak

...\cla16Bit.v

...\cla32Bit.v

...\cla64Bit.v

...\cla8Bit.v

...\compare.v

...\compare16.v

...\compare32.v

...\compare32.v.bak

...\compare8.v

...\compare8.v.bak

...\compare80.v

...\ConInt16ToSP.v

...\ConInt16ToSP.v.bak

...\ConInt32ToSP.v

...\ConInt64ToSP.v

...\conUnitWrapper.v

...\conUnitWrapper.v.bak

...\Convert32.v

...\Convert64.v

...\Convert80To32.v

...\Convert80To64.v

...\ConvertSPTo16Int.v

...\ConvertSPTo32Int.v

...\ConvertSPTo64Int.v

...\DataFlow.v

...\division.v

...\division64.v

...\division64.v.bak

...\fdiv.v

...\fmul.v

...\fpuAlu.v

...\FxamNumber.v

...\mmxalu.v

...\mul64.v

...\mul64.v.bak

...\multiply32.v

...\multiply32.v.bak

...\pop.v

...\RegFile.v

...\Register_XMM.v

...\rotate.v

...\rotateWithCarry.v

...\shift16Arith.v

...\shift32Arith.v

...\shift64Arith.v

...\shiftArith.v

...\shiftLogical.v

...\shift_16_Logical.v

...\shift_32_Logical.v

...\shift_64_Logical.v

...\shld.v

...\shrd.v

...\sse2alu.v

...\sse2alu.v.bak

...\sse2Decoder.v

...\sse3Alu.v

...\sse3Decoder.v

...\TaskSwitch.v

...\TwosPower.v

...\twos_compl.v

...\XMM_Registers.v

hdl