文件名称:UART
介绍说明－－下载内容均来自于网络，请自行研究使用
串行接口芯片的设计。本程序是在ISE开发环境中编写的UART串行通信接口。适合初学者的学习。-Serial interface chip designs. The program is written in the ISE development environment in the UART serial communication interface. For beginners to learn.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
UART\UART.ise
....\__ISE_repository_UART.ise_.lock
....\UART.restore
....\parity_verifier.prj
....\parity_verifier.xst
....\parity_verifier.stx
....\.lso
....\shift_reg.prj
....\_xmsgs\ngdbuild.xmsgs
....\......\map.xmsgs
....\......\par.xmsgs
....\......\trce.xmsgs
....\......\netgen.xmsgs
....\......\bitgen.xmsgs
....\......\xst.xmsgs
....\......\fuse.xmsgs
....\UART.ise_ISE_Backup
....\shift_reg.xst
....\shift_reg.stx
....\switcher_bus.prj
....\switcher_bus.xst
....\switcher_bus.stx
....\uart_core.prj
....\uart_core.xst
....\uart_core.stx
....\uart_top.v
....\uart_top_summary.html
....\uart_top.prj
....\uart_top.xst
....\uart_top.stx
....\test_uart_v.v
....\test_uart_v_summary.html
....\test_uart_v.prj
....\test_uart_v.xst
....\test_uart_v.stx
....\xilinxsim.ini
....\test_uart_v_stx.prj
....\isim\temp\vlg24\uart__core.bin
....\....\....\hdllib.ref
....\....\....\vlg62\switcher__bus.bin
....\....\....\...43\shift__reg.bin
....\....\....\...64\parity__verifier.bin
....\....\....\...02\detector.bin
....\....\....\...10\counter.bin
....\....\....\....6\baudrate__generator.bin
....\....\....\....A\uart__top.bin
....\....\....\...54\test__uart__v.bin
....\....\....\...2D\glbl.bin
....\....\....\...7E\test1__v.bin
....\....\....\...17\test2__v.bin
....\....\....\...30\test3__v.bin
....\....\....\hdpdeps.ref
....\....\work\vlg24\uart__core.bin
....\....\....\hdllib.ref
....\....\....\uart__core\uart__core.h
....\....\....\..........\mingw\uart__core.obj
....\....\....\vlg62\switcher__bus.bin
....\....\....\switcher__bus\switcher__bus.h
....\....\....\.............\mingw\switcher__bus.obj
....\....\....\vlg43\shift__reg.bin
....\....\....\shift__reg\shift__reg.h
....\....\....\..........\mingw\shift__reg.obj
....\....\....\vlg64\parity__verifier.bin
....\....\....\parity__verifier\parity__verifier.h
....\....\....\................\mingw\parity__verifier.obj
....\....\....\vlg02\detector.bin
....\....\....\detector\detector.h
....\....\....\........\mingw\detector.obj
....\....\....\........\xsimdetector.cpp
....\....\....\vlg10\counter.bin
....\....\....\counter\counter.h
....\....\....\.......\mingw\counter.obj
....\....\....\.......\xsimcounter.cpp
....\....\....\vlg16\baudrate__generator.bin
....\....\....\baudrate__generator\baudrate__generator.h
....\....\....\...................\mingw\baudrate__generator.obj
....\....\....\...................\xsimbaudrate__generator.cpp
....\....\....\vlg1A\uart__top.bin
....\....\....\uart__top\uart__top.h
....\....\....\.........\mingw\uart__top.obj
....\....\....\.........\xsimuart__top.cpp
....\....\....\vlg54\test__uart__v.bin
....\....\....\test__uart__v\test__uart__v.h
....\....\....\.............\mingw\test__uart__v.obj
....\....\....\.............\xsimtest__uart__v.cpp
....\....\....\vlg2D\glbl.bin
....\....\....\glbl\glbl.h
....\....\....\....\mingw\glbl.obj
....\....\....\vlg7E\test1__v.bin
....\....\....\test1__v\test1__v.h
....\....\....\........\mingw\test1__v.obj
....\....\....\........\xsimtest1__v.cpp
....\....\....\vlg17\test2__v.bin
....\....\....\test2__v\test2__v.h
....\....\....\........\mingw\test2__v.obj
....\....\....\........\xsimtest2__v.cpp
....\....\....\vlg30\test3__v.bin
....\....\....\test3__v\test3__v.h
....\....\....\........\mingw\test3__v.obj
....\....\....\........\xsimtest3__v.cpp
....\__ISE_repository_UART.ise_.lock
....\UART.restore
....\parity_verifier.prj
....\parity_verifier.xst
....\parity_verifier.stx
....\.lso
....\shift_reg.prj
....\_xmsgs\ngdbuild.xmsgs
....\......\map.xmsgs
....\......\par.xmsgs
....\......\trce.xmsgs
....\......\netgen.xmsgs
....\......\bitgen.xmsgs
....\......\xst.xmsgs
....\......\fuse.xmsgs
....\UART.ise_ISE_Backup
....\shift_reg.xst
....\shift_reg.stx
....\switcher_bus.prj
....\switcher_bus.xst
....\switcher_bus.stx
....\uart_core.prj
....\uart_core.xst
....\uart_core.stx
....\uart_top.v
....\uart_top_summary.html
....\uart_top.prj
....\uart_top.xst
....\uart_top.stx
....\test_uart_v.v
....\test_uart_v_summary.html
....\test_uart_v.prj
....\test_uart_v.xst
....\test_uart_v.stx
....\xilinxsim.ini
....\test_uart_v_stx.prj
....\isim\temp\vlg24\uart__core.bin
....\....\....\hdllib.ref
....\....\....\vlg62\switcher__bus.bin
....\....\....\...43\shift__reg.bin
....\....\....\...64\parity__verifier.bin
....\....\....\...02\detector.bin
....\....\....\...10\counter.bin
....\....\....\....6\baudrate__generator.bin
....\....\....\....A\uart__top.bin
....\....\....\...54\test__uart__v.bin
....\....\....\...2D\glbl.bin
....\....\....\...7E\test1__v.bin
....\....\....\...17\test2__v.bin
....\....\....\...30\test3__v.bin
....\....\....\hdpdeps.ref
....\....\work\vlg24\uart__core.bin
....\....\....\hdllib.ref
....\....\....\uart__core\uart__core.h
....\....\....\..........\mingw\uart__core.obj
....\....\....\vlg62\switcher__bus.bin
....\....\....\switcher__bus\switcher__bus.h
....\....\....\.............\mingw\switcher__bus.obj
....\....\....\vlg43\shift__reg.bin
....\....\....\shift__reg\shift__reg.h
....\....\....\..........\mingw\shift__reg.obj
....\....\....\vlg64\parity__verifier.bin
....\....\....\parity__verifier\parity__verifier.h
....\....\....\................\mingw\parity__verifier.obj
....\....\....\vlg02\detector.bin
....\....\....\detector\detector.h
....\....\....\........\mingw\detector.obj
....\....\....\........\xsimdetector.cpp
....\....\....\vlg10\counter.bin
....\....\....\counter\counter.h
....\....\....\.......\mingw\counter.obj
....\....\....\.......\xsimcounter.cpp
....\....\....\vlg16\baudrate__generator.bin
....\....\....\baudrate__generator\baudrate__generator.h
....\....\....\...................\mingw\baudrate__generator.obj
....\....\....\...................\xsimbaudrate__generator.cpp
....\....\....\vlg1A\uart__top.bin
....\....\....\uart__top\uart__top.h
....\....\....\.........\mingw\uart__top.obj
....\....\....\.........\xsimuart__top.cpp
....\....\....\vlg54\test__uart__v.bin
....\....\....\test__uart__v\test__uart__v.h
....\....\....\.............\mingw\test__uart__v.obj
....\....\....\.............\xsimtest__uart__v.cpp
....\....\....\vlg2D\glbl.bin
....\....\....\glbl\glbl.h
....\....\....\....\mingw\glbl.obj
....\....\....\vlg7E\test1__v.bin
....\....\....\test1__v\test1__v.h
....\....\....\........\mingw\test1__v.obj
....\....\....\........\xsimtest1__v.cpp
....\....\....\vlg17\test2__v.bin
....\....\....\test2__v\test2__v.h
....\....\....\........\mingw\test2__v.obj
....\....\....\........\xsimtest2__v.cpp
....\....\....\vlg30\test3__v.bin
....\....\....\test3__v\test3__v.h
....\....\....\........\mingw\test3__v.obj
....\....\....\........\xsimtest3__v.cpp