文件名称:8bitcpu_microprogrammed_vhdl
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八位微程序结构的cpu设计 。 此为课堂设计，欢迎大家参考。 本人联系方式：justin_dengcn@126.com-8 cpu micro-structure of the design process. This is a lesson. please Contact: justin_dengcn@126.com
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下载文件列表
Finial(20100415)\ACC.bsf
................\ACC.vhd
................\ACCTest.bdf
................\ACCtest.vwf
................\BR.bsf
................\BR.vhd
................\cmp_state.ini
................\ControlMem32Ini.mif
................\ControlMemBDF.bdf
................\ControlMemory.bsf
................\ControlMemory.v
................\ControlMemoryIni.mif
................\ControlMemory_bb.v
................\controlMemWave.vwf
................\ControlUnit.bsf
................\ControlUnit.vhd
................\ControlUnitBlock.bdf
................\CPU-Top.bdf
................\CPU.qpf
................\CPU.qws
................\CPUDesign.asm.rpt
................\CPUDesign.done
................\CPUDesign.fit.eqn
................\CPUDesign.fit.rpt
................\CPUDesign.fit.summary
................\CPUDesign.flow.rpt
................\CPUDesign.map.eqn
................\CPUDesign.map.rpt
................\CPUDesign.map.summary
................\CPUDesign.pin
................\CPUDesign.pof
................\CPUDesign.qsf
................\CPUDesign.sim.rpt
................\CPUDesign.sof
................\CPUDesign.tan.rpt
................\CPUDesign.tan.summary
................\CPUTOPWAVE.vwf
................\db\add_sub_0qh.tdf
................\..\add_sub_1qh.tdf
................\..\add_sub_5sh.tdf
................\..\add_sub_lth.tdf
................\..\altsyncram_d3r.tdf
................\..\altsyncram_n8j.tdf
................\..\altsyncram_nc31.tdf
................\..\altsyncram_o8j.tdf
................\..\altsyncram_p8j.tdf
................\..\altsyncram_q8j.tdf
................\..\altsyncram_r8j.tdf
................\..\altsyncram_rrq.tdf
................\..\altsyncram_s511.tdf
................\..\CPU-Top0.rtl.mif
................\..\CPU-Top1.rtl.mif
................\..\CPUDesign.asm.qmsg
................\..\CPUDesign.cbx.xml
................\..\CPUDesign.cmp.rdb
................\..\CPUDesign.db_info
................\..\CPUDesign.eco.cdb
................\..\CPUDesign.eds_overflow
................\..\CPUDesign.fit.qmsg
................\..\CPUDesign.fnsim.cdb
................\..\CPUDesign.fnsim.hdb
................\..\CPUDesign.hier_info
................\..\CPUDesign.hif
................\..\CPUDesign.map.cdb
................\..\CPUDesign.map.hdb
................\..\CPUDesign.map.logdb
................\..\CPUDesign.map.qmsg
................\..\CPUDesign.pre_map.cdb
................\..\CPUDesign.pre_map.hdb
................\..\CPUDesign.psp
................\..\CPUDesign.rtlv.hdb
................\..\CPUDesign.rtlv_sg.cdb
................\..\CPUDesign.rtlv_sg_swap.cdb
................\..\CPUDesign.sgdiff.cdb
................\..\CPUDesign.sgdiff.hdb
................\..\CPUDesign.sim.hdb
................\..\CPUDesign.sim.qmsg
................\..\CPUDesign.sim.rdb
................\..\CPUDesign.sim.vwf
................\..\CPUDesign.sld_design_entry.sci
................\..\CPUDesign.sld_design_entry_dsc.sci
................\..\CPUDesign.syn_hier_info
................\..\CPUDesign.tan.qmsg
................\..\CPUDesign_cmp.qrpt
................\..\CPUDesign_sim.qrpt
................\IR.bsf
................\IR.vhd
................\MAR.bsf
................\MAR.vhd
................\MBR.bsf
................\MBR.vhd
................\MBR_Test.bdf
................\MBR_testWAVE.vwf
................\moto-txt.jad
................\MPY.bdf
................\mpy.vwf
................\MR.bsf
................\MR.vhd
................\mulxxx.vhd
................\PC.bsf
................\ACC.vhd
................\ACCTest.bdf
................\ACCtest.vwf
................\BR.bsf
................\BR.vhd
................\cmp_state.ini
................\ControlMem32Ini.mif
................\ControlMemBDF.bdf
................\ControlMemory.bsf
................\ControlMemory.v
................\ControlMemoryIni.mif
................\ControlMemory_bb.v
................\controlMemWave.vwf
................\ControlUnit.bsf
................\ControlUnit.vhd
................\ControlUnitBlock.bdf
................\CPU-Top.bdf
................\CPU.qpf
................\CPU.qws
................\CPUDesign.asm.rpt
................\CPUDesign.done
................\CPUDesign.fit.eqn
................\CPUDesign.fit.rpt
................\CPUDesign.fit.summary
................\CPUDesign.flow.rpt
................\CPUDesign.map.eqn
................\CPUDesign.map.rpt
................\CPUDesign.map.summary
................\CPUDesign.pin
................\CPUDesign.pof
................\CPUDesign.qsf
................\CPUDesign.sim.rpt
................\CPUDesign.sof
................\CPUDesign.tan.rpt
................\CPUDesign.tan.summary
................\CPUTOPWAVE.vwf
................\db\add_sub_0qh.tdf
................\..\add_sub_1qh.tdf
................\..\add_sub_5sh.tdf
................\..\add_sub_lth.tdf
................\..\altsyncram_d3r.tdf
................\..\altsyncram_n8j.tdf
................\..\altsyncram_nc31.tdf
................\..\altsyncram_o8j.tdf
................\..\altsyncram_p8j.tdf
................\..\altsyncram_q8j.tdf
................\..\altsyncram_r8j.tdf
................\..\altsyncram_rrq.tdf
................\..\altsyncram_s511.tdf
................\..\CPU-Top0.rtl.mif
................\..\CPU-Top1.rtl.mif
................\..\CPUDesign.asm.qmsg
................\..\CPUDesign.cbx.xml
................\..\CPUDesign.cmp.rdb
................\..\CPUDesign.db_info
................\..\CPUDesign.eco.cdb
................\..\CPUDesign.eds_overflow
................\..\CPUDesign.fit.qmsg
................\..\CPUDesign.fnsim.cdb
................\..\CPUDesign.fnsim.hdb
................\..\CPUDesign.hier_info
................\..\CPUDesign.hif
................\..\CPUDesign.map.cdb
................\..\CPUDesign.map.hdb
................\..\CPUDesign.map.logdb
................\..\CPUDesign.map.qmsg
................\..\CPUDesign.pre_map.cdb
................\..\CPUDesign.pre_map.hdb
................\..\CPUDesign.psp
................\..\CPUDesign.rtlv.hdb
................\..\CPUDesign.rtlv_sg.cdb
................\..\CPUDesign.rtlv_sg_swap.cdb
................\..\CPUDesign.sgdiff.cdb
................\..\CPUDesign.sgdiff.hdb
................\..\CPUDesign.sim.hdb
................\..\CPUDesign.sim.qmsg
................\..\CPUDesign.sim.rdb
................\..\CPUDesign.sim.vwf
................\..\CPUDesign.sld_design_entry.sci
................\..\CPUDesign.sld_design_entry_dsc.sci
................\..\CPUDesign.syn_hier_info
................\..\CPUDesign.tan.qmsg
................\..\CPUDesign_cmp.qrpt
................\..\CPUDesign_sim.qrpt
................\IR.bsf
................\IR.vhd
................\MAR.bsf
................\MAR.vhd
................\MBR.bsf
................\MBR.vhd
................\MBR_Test.bdf
................\MBR_testWAVE.vwf
................\moto-txt.jad
................\MPY.bdf
................\mpy.vwf
................\MR.bsf
................\MR.vhd
................\mulxxx.vhd
................\PC.bsf