文件名称:ml505_mig_design
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Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
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下载文件列表
ml505_mig_design\mig_30.gise
................\mig_30.ise
................\mig_30.veo
................\mig_30.xco
................\mig_30.xise
................\......\docs\adr_cntrl_timing.xls
................\......\....\read_data_timing.xls
................\......\....\ug086.pdf
................\......\....\write_data_timing.xls
................\......\example_design\datasheet.txt
................\......\..............\log.txt
................\......\..............\mig.prj
................\......\..............\par\chipscope.cpj
................\......\..............\...\create_ise.bat
................\......\..............\...\icon.ngc
................\......\..............\...\icon.v
................\......\..............\...\icon.veo
................\......\..............\...\icon.xco
................\......\..............\...\icon4_cg.xco
................\......\..............\...\icon_flist.txt
................\......\..............\...\icon_readme.txt
................\......\..............\...\icon_xmdf.tcl
................\......\..............\...\ila.cdc
................\......\..............\...\ila.ngc
................\......\..............\...\ila.v
................\......\..............\...\ila.veo
................\......\..............\...\ila.xco
................\......\..............\...\ila_flist.txt
................\......\..............\...\ila_readme.txt
................\......\..............\...\ila_xmdf.tcl
................\......\..............\...\ise_flow.bat
................\......\..............\...\ise_flow_results.txt
................\......\..............\...\mem_interface_top.ut
................\......\..............\...\mig_30.bit
................\......\..............\...\mig_30.bld
................\......\..............\...\mig_30.pad
................\......\..............\...\mig_30.par
................\......\..............\...\mig_30.ucf
................\......\..............\...\readme.txt
................\......\..............\...\rem_files.bat
................\......\..............\...\set_ise_prop.tcl
................\......\..............\...\vio_async_in100_cg.xco
................\......\..............\...\vio_async_in192_cg.xco
................\......\..............\...\vio_async_in96_cg.xco
................\......\..............\...\vio_sync_out32_cg.xco
................\......\..............\...\xst_run.txt
................\......\..............\rtl\ddr2_chipscope.v
................\......\..............\...\ddr2_ctrl.v
................\......\..............\...\ddr2_idelay_ctrl.v
................\......\..............\...\ddr2_infrastructure.v
................\......\..............\...\ddr2_mem_if_top.v
................\......\..............\...\ddr2_phy_calib.v
................\......\..............\...\ddr2_phy_ctl_io.v
................\......\..............\...\ddr2_phy_dm_iob.v
................\......\..............\...\ddr2_phy_dq_iob.v
................\......\..............\...\ddr2_phy_dqs_iob.v
................\......\..............\...\ddr2_phy_init.v
................\......\..............\...\ddr2_phy_io.v
................\......\..............\...\ddr2_phy_top.v
................\......\..............\...\ddr2_phy_write.v
................\......\..............\...\ddr2_tb_test_addr_gen.v
................\......\..............\...\ddr2_tb_test_cmp.v
................\......\..............\...\ddr2_tb_test_data_gen.v
................\......\..............\...\ddr2_tb_test_gen.v
................\......\..............\...\ddr2_tb_top.v
................\......\..............\...\ddr2_top.v
................\......\..............\...\ddr2_usr_addr_fifo.v
................\......\..............\...\ddr2_usr_rd.v
................\......\..............\...\ddr2_usr_top.v
................\......\..............\...\ddr2_usr_wr.v
................\......\..............\...\mig_30.v
................\......\..............\...\mig_30_chipscope.v
................\......\..............\sim\glbl.v
................\......\..............\...\sim.do
................\......\..............\
................\mig_30.ise
................\mig_30.veo
................\mig_30.xco
................\mig_30.xise
................\......\docs\adr_cntrl_timing.xls
................\......\....\read_data_timing.xls
................\......\....\ug086.pdf
................\......\....\write_data_timing.xls
................\......\example_design\datasheet.txt
................\......\..............\log.txt
................\......\..............\mig.prj
................\......\..............\par\chipscope.cpj
................\......\..............\...\create_ise.bat
................\......\..............\...\icon.ngc
................\......\..............\...\icon.v
................\......\..............\...\icon.veo
................\......\..............\...\icon.xco
................\......\..............\...\icon4_cg.xco
................\......\..............\...\icon_flist.txt
................\......\..............\...\icon_readme.txt
................\......\..............\...\icon_xmdf.tcl
................\......\..............\...\ila.cdc
................\......\..............\...\ila.ngc
................\......\..............\...\ila.v
................\......\..............\...\ila.veo
................\......\..............\...\ila.xco
................\......\..............\...\ila_flist.txt
................\......\..............\...\ila_readme.txt
................\......\..............\...\ila_xmdf.tcl
................\......\..............\...\ise_flow.bat
................\......\..............\...\ise_flow_results.txt
................\......\..............\...\mem_interface_top.ut
................\......\..............\...\mig_30.bit
................\......\..............\...\mig_30.bld
................\......\..............\...\mig_30.pad
................\......\..............\...\mig_30.par
................\......\..............\...\mig_30.ucf
................\......\..............\...\readme.txt
................\......\..............\...\rem_files.bat
................\......\..............\...\set_ise_prop.tcl
................\......\..............\...\vio_async_in100_cg.xco
................\......\..............\...\vio_async_in192_cg.xco
................\......\..............\...\vio_async_in96_cg.xco
................\......\..............\...\vio_sync_out32_cg.xco
................\......\..............\...\xst_run.txt
................\......\..............\rtl\ddr2_chipscope.v
................\......\..............\...\ddr2_ctrl.v
................\......\..............\...\ddr2_idelay_ctrl.v
................\......\..............\...\ddr2_infrastructure.v
................\......\..............\...\ddr2_mem_if_top.v
................\......\..............\...\ddr2_phy_calib.v
................\......\..............\...\ddr2_phy_ctl_io.v
................\......\..............\...\ddr2_phy_dm_iob.v
................\......\..............\...\ddr2_phy_dq_iob.v
................\......\..............\...\ddr2_phy_dqs_iob.v
................\......\..............\...\ddr2_phy_init.v
................\......\..............\...\ddr2_phy_io.v
................\......\..............\...\ddr2_phy_top.v
................\......\..............\...\ddr2_phy_write.v
................\......\..............\...\ddr2_tb_test_addr_gen.v
................\......\..............\...\ddr2_tb_test_cmp.v
................\......\..............\...\ddr2_tb_test_data_gen.v
................\......\..............\...\ddr2_tb_test_gen.v
................\......\..............\...\ddr2_tb_top.v
................\......\..............\...\ddr2_top.v
................\......\..............\...\ddr2_usr_addr_fifo.v
................\......\..............\...\ddr2_usr_rd.v
................\......\..............\...\ddr2_usr_top.v
................\......\..............\...\ddr2_usr_wr.v
................\......\..............\...\mig_30.v
................\......\..............\...\mig_30_chipscope.v
................\......\..............\sim\glbl.v
................\......\..............\...\sim.do
................\......\..............\