文件名称:100vhdlsimple
介绍说明－－下载内容均来自于网络，请自行研究使用
100个vhdl例子，对初学者很有用，可以用MAX+PLUS 2来编译仿真的-100 vhdl example, useful for beginners, you can use the MAX+ PLUS 2 to compile the simulation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
100vhdl例子\10_function\10_bit_to_int.vhd
...........\...........\README.TXT
...........\10_function
...........\.1_wiredor\11_wiredor.vhd
...........\..........\README.TXT
...........\11_wiredor
...........\.2_convert\12_convert.vhd
...........\..........\README.TXT
...........\12_convert
...........\.3_SHL\13_SHL.VHD
...........\......\README.TXT
...........\13_SHL
...........\.4_MVL7_functions\14_MVL7_functions.vhd
...........\.................\README.TXT
...........\14_MVL7_functions
...........\.5_MUX41\15_MUX41.VHD
...........\........\15_MVL7_functions.vhd
...........\........\15_MVL7_syn_types.vhd
...........\........\15_test_vectors_mux41.vhd
...........\........\15_TYPES.VHD
...........\........\README.TXT
...........\15_MUX41
...........\.6_MUX\16_multiple_mux.vhd
...........\......\16_MVL7_functions.vhd
...........\......\16_test_vectors.vhd
...........\......\16_TYPES.VHD
...........\......\README.TXT
...........\......\TYPES.VHD
...........\16_MUX
...........\.7_parity\17_parity.vhd
...........\.........\17_test_bench.vhd
...........\.........\README.TXT
...........\17_parity
...........\.8_LIB\18_tech_lib.vhd
...........\......\18_test_lib.vhd
...........\......\README.TXT
...........\18_LIB
...........\.9_test_194\19_test_194.vhd
...........\19_test_194
...........\._ADDER\1_ADDER\1_ADDER.exp
...........\.......\.......\files\L1.rpt
...........\.......\.......\.....\L2.rpt
...........\.......\.......\.....\L3.rpt
...........\.......\.......\files
...........\.......\.......\workdirs\aa\ADDER.sim
...........\.......\.......\........\..\ADDER.syn
...........\.......\.......\........\..\Anal.info
...........\.......\.......\........\..\Anal.out
...........\.......\.......\........\aa
...........\.......\.......\........\WORK\Anal.info
...........\.......\.......\........\....\Anal.out
...........\.......\.......\........\....\BIT_RTL_ADDER.sim
...........\.......\.......\........\....\BIT_RTL_ADDER.syn
...........\.......\.......\........\WORK
...........\.......\.......\workdirs
...........\.......\1_ADDER
...........\.......\1_adder.acf
...........\.......\1_adder.hif
...........\.......\1_adder.mmf
...........\.......\1_ADDER.VHD
...........\.......\bir_rtl_adder.acf
...........\.......\bir_rtl_adder.hif
...........\.......\bir_rtl_adder.mmf
...........\.......\bir_rtl_adder.tdf
...........\.......\bit_rtl_adder.acf
...........\.......\bit_rtl_adder.hif
...........\.......\bit_rtl_adder.mmf
...........\.......\bit_rtl_adder.vhd
...........\.......\LIB.DLS
...........\.......\README.TXT
...........\.......\U2268397.DLS
...........\1_ADDER
...........\20_test_159\20_test_159.vhd
...........\20_test_159
...........\.1_test_13a\21_test_13a.vhd
...........\21_test_13a
...........\.2_deadlock\22_deadlock.vhd
...........\22_deadlock
...........\.3_test_120\23_Test_120.vhd
...........\23_test_120
...........\.4_test_195\24_test_195.vhd
...........\24_test_195
...........\.5_test_1\25_test_1.vhd
...........\.........\25_test_1a.vhd
...........\25_test_1
...........\.6_test_74s\26_test_74s.vhd
...........\26_test_74s
...........\.7_test_16\27_test_16.vhd
...........\27_test_16
...........\.8_test_64a\28_Test_64a.vhd
...........\28_test_64a
...........\.9_test_35\29_Test_35.vhd
...........\29_test_35
...........\._ADDER\2_ADDER.VHD
...........\.......\README.TXT
...........\2_ADDER
...........\30_test_3\30_Test_3.vhd
...........\30_test_3
...........\.1_test_35b\31_test_35b.vhd
...........\31_test_35b
...........\...........\README.TXT
...........\10_function
...........\.1_wiredor\11_wiredor.vhd
...........\..........\README.TXT
...........\11_wiredor
...........\.2_convert\12_convert.vhd
...........\..........\README.TXT
...........\12_convert
...........\.3_SHL\13_SHL.VHD
...........\......\README.TXT
...........\13_SHL
...........\.4_MVL7_functions\14_MVL7_functions.vhd
...........\.................\README.TXT
...........\14_MVL7_functions
...........\.5_MUX41\15_MUX41.VHD
...........\........\15_MVL7_functions.vhd
...........\........\15_MVL7_syn_types.vhd
...........\........\15_test_vectors_mux41.vhd
...........\........\15_TYPES.VHD
...........\........\README.TXT
...........\15_MUX41
...........\.6_MUX\16_multiple_mux.vhd
...........\......\16_MVL7_functions.vhd
...........\......\16_test_vectors.vhd
...........\......\16_TYPES.VHD
...........\......\README.TXT
...........\......\TYPES.VHD
...........\16_MUX
...........\.7_parity\17_parity.vhd
...........\.........\17_test_bench.vhd
...........\.........\README.TXT
...........\17_parity
...........\.8_LIB\18_tech_lib.vhd
...........\......\18_test_lib.vhd
...........\......\README.TXT
...........\18_LIB
...........\.9_test_194\19_test_194.vhd
...........\19_test_194
...........\._ADDER\1_ADDER\1_ADDER.exp
...........\.......\.......\files\L1.rpt
...........\.......\.......\.....\L2.rpt
...........\.......\.......\.....\L3.rpt
...........\.......\.......\files
...........\.......\.......\workdirs\aa\ADDER.sim
...........\.......\.......\........\..\ADDER.syn
...........\.......\.......\........\..\Anal.info
...........\.......\.......\........\..\Anal.out
...........\.......\.......\........\aa
...........\.......\.......\........\WORK\Anal.info
...........\.......\.......\........\....\Anal.out
...........\.......\.......\........\....\BIT_RTL_ADDER.sim
...........\.......\.......\........\....\BIT_RTL_ADDER.syn
...........\.......\.......\........\WORK
...........\.......\.......\workdirs
...........\.......\1_ADDER
...........\.......\1_adder.acf
...........\.......\1_adder.hif
...........\.......\1_adder.mmf
...........\.......\1_ADDER.VHD
...........\.......\bir_rtl_adder.acf
...........\.......\bir_rtl_adder.hif
...........\.......\bir_rtl_adder.mmf
...........\.......\bir_rtl_adder.tdf
...........\.......\bit_rtl_adder.acf
...........\.......\bit_rtl_adder.hif
...........\.......\bit_rtl_adder.mmf
...........\.......\bit_rtl_adder.vhd
...........\.......\LIB.DLS
...........\.......\README.TXT
...........\.......\U2268397.DLS
...........\1_ADDER
...........\20_test_159\20_test_159.vhd
...........\20_test_159
...........\.1_test_13a\21_test_13a.vhd
...........\21_test_13a
...........\.2_deadlock\22_deadlock.vhd
...........\22_deadlock
...........\.3_test_120\23_Test_120.vhd
...........\23_test_120
...........\.4_test_195\24_test_195.vhd
...........\24_test_195
...........\.5_test_1\25_test_1.vhd
...........\.........\25_test_1a.vhd
...........\25_test_1
...........\.6_test_74s\26_test_74s.vhd
...........\26_test_74s
...........\.7_test_16\27_test_16.vhd
...........\27_test_16
...........\.8_test_64a\28_Test_64a.vhd
...........\28_test_64a
...........\.9_test_35\29_Test_35.vhd
...........\29_test_35
...........\._ADDER\2_ADDER.VHD
...........\.......\README.TXT
...........\2_ADDER
...........\30_test_3\30_Test_3.vhd
...........\30_test_3
...........\.1_test_35b\31_test_35b.vhd
...........\31_test_35b