文件名称:digital-frequency

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.21mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • multid******
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数字频率计

采用Verilog语言编写,分为8个模块,分别是计数器,门控,分频,寄存器,多路选择,动态位选择,BCD译码模块-Digital frequency meter using Verilog language, divided into eight modules, namely, the counter, gated, frequency, register, multiplexer, Dynamic Choice, BCD decoding module
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下载文件列表

第4章\counter\cmp_state.ini

.....\.......\counter.asm.rpt

.....\.......\counter.bsf

.....\.......\counter.done

.....\.......\counter.fit.eqn

.....\.......\counter.fit.rpt

.....\.......\counter.fit.summary

.....\.......\counter.flow.rpt

.....\.......\counter.map.eqn

.....\.......\counter.map.rpt

.....\.......\counter.map.summary

.....\.......\counter.pin

.....\.......\counter.pof

.....\.......\counter.qpf

.....\.......\counter.qsf

.....\.......\counter.qws

.....\.......\counter.sim.rpt

.....\.......\counter.tan.rpt

.....\.......\counter.tan.summary

.....\.......\counter.v

.....\.......\counter.vwf

.....\.......\counter10.v

.....\.......\db\counter.asm.qmsg

.....\.......\..\counter.cmp.cdb

.....\.......\..\counter.cmp.ddb

.....\.......\..\counter.cmp.hdb

.....\.......\..\counter.cmp.rdb

.....\.......\..\counter.cmp.tdb

.....\.......\..\counter.cmp0.ddb

.....\.......\..\counter.db_info

.....\.......\..\counter.eco.cdb

.....\.......\..\counter.eds_overflow

.....\.......\..\counter.fit.qmsg

.....\.......\..\counter.hier_info

.....\.......\..\counter.hif

.....\.......\..\counter.map.cdb

.....\.......\..\counter.map.hdb

.....\.......\..\counter.map.qmsg

.....\.......\..\counter.pre_map.cdb

.....\.......\..\counter.pre_map.hdb

.....\.......\..\counter.psp

.....\.......\..\counter.rtlv.hdb

.....\.......\..\counter.rtlv_sg.cdb

.....\.......\..\counter.rtlv_sg_swap.cdb

.....\.......\..\counter.sgdiff.cdb

.....\.......\..\counter.sgdiff.hdb

.....\.......\..\counter.sim.hdb

.....\.......\..\counter.sim.qmsg

.....\.......\..\counter.sim.rdb

.....\.......\..\counter.sim.vwf

.....\.......\..\counter.sld_design_entry.sci

.....\.......\..\counter.sld_design_entry_dsc.sci

.....\.......\..\counter.syn_hier_info

.....\.......\..\counter.tan.qmsg

.....\.......\..\counter_cmp.qrpt

.....\.......\..\counter_sim.qrpt

.....\.......\Waveform1.vwf

.....\data_mux\cmp_state.ini

.....\........\data_mux.asm.rpt

.....\........\data_mux.bsf

.....\........\data_mux.done

.....\........\data_mux.fit.eqn

.....\........\data_mux.fit.rpt

.....\........\data_mux.fit.summary

.....\........\data_mux.flow.rpt

.....\........\data_mux.map.eqn

.....\........\data_mux.map.rpt

.....\........\data_mux.map.summary

.....\........\data_mux.pin

.....\........\data_mux.pof

.....\........\data_mux.qpf

.....\........\data_mux.qsf

.....\........\data_mux.qws

.....\........\data_mux.sim.rpt

.....\........\data_mux.tan.rpt

.....\........\data_mux.tan.summary

.....\........\data_mux.v

.....\........\data_mux.vwf

.....\........\.b\data_mux.asm.qmsg

.....\........\..\data_mux.cmp.cdb

.....\........\..\data_mux.cmp.ddb

.....\........\..\data_mux.cmp.hdb

.....\........\..\data_mux.cmp.rdb

.....\........\..\data_mux.cmp.tdb

.....\........\..\data_mux.cmp0.ddb

.....\........\..\data_mux.db_info

.....\........\..\data_mux.eco.cdb

.....\........\..\data_mux.eds_overflow

.....\........\..\data_mux.fit.qmsg

.....\........\..\data_mux.hier_info

.....\........\..\data_mux.hif

.....\........\..\data_mux.map.cdb

.....\........\..\data_mux.map.hdb

.....\........\..\data_mux.map.qmsg

.....\........\..\data_mux.pre_map.cdb

.....\........\..\data_mux.pre_map.hdb

.....\........\..\data_mux.psp

.....\........\..\data_mux.rtlv.hdb

.....\........\..\data_mux.rtlv_sg.cdb

.....\........\..\data_mux.rtlv_sg_swap.cdb

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