文件名称:PipelineCPU
介绍说明－－下载内容均来自于网络，请自行研究使用
用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
流水线源文件\adder.v
............\adder4.v
............\alu16.v
............\ALU_control.v
............\control_new.v
............\cpu.bdf
............\cpu.vwf
............\Data_mem.v
............\EXMEM.v
............\IDEX.v
............\IFID.v
............\ins.txt
............\Ins_mem.v
............\ins_qs.txt
............\jal.v
............\maoxian.v
............\MEMWB.v
............\mux3.v
............\Mux32_2.v
............\Mux32_4.v
............\Mux5.v
............\mux_2.v
............\PC.v
............\Registers.v
............\same.v
............\sign_extend.v
............\sign_extend2.v
............\sl2.v
............\sll2.v
............\zhuanfa.v
............\说明.txt
流水线源文件
............\adder4.v
............\alu16.v
............\ALU_control.v
............\control_new.v
............\cpu.bdf
............\cpu.vwf
............\Data_mem.v
............\EXMEM.v
............\IDEX.v
............\IFID.v
............\ins.txt
............\Ins_mem.v
............\ins_qs.txt
............\jal.v
............\maoxian.v
............\MEMWB.v
............\mux3.v
............\Mux32_2.v
............\Mux32_4.v
............\Mux5.v
............\mux_2.v
............\PC.v
............\Registers.v
............\same.v
............\sign_extend.v
............\sign_extend2.v
............\sl2.v
............\sll2.v
............\zhuanfa.v
............\说明.txt
流水线源文件