文件名称:manch
介绍说明－－下载内容均来自于网络，请自行研究使用
该文件是一个完整的工程文件，用VerilogHDL语言编写，包括曼彻斯特编码器的设计文件和仿真测试文件以及解码器的设计文件和仿真测试文件。在Modelsim中仿真测试通过。-The document is a complete project file, with VerilogHDL languages, including the Manchester encoder design documents and simulation test files and decoder design documents and simulation test file. In the Modelsim simulation test.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
4.2\manch_de.rpt
...\manch_de.v
...\manch_de_testbench.v
...\manch_en.rpt
...\manch_en.v
...\manch_en_de.cr.mti
...\manch_en_de.mpf
...\manch_en_de.v
...\manch_en_testbench.v
...\transcript
...\vsim.wlf
...\chart\Thumbs.db
...\.....\图4-5.bmp
...\.....\图4-7.bmp
...\wave\Thumbs.db
...\....\manch_de.bmp
...\....\manch_de_testbench.bmp
...\....\manch_en.bmp
...\....\manch_en_testbench.bmp
...\.ork\_info
...\....\manch_de\_primary.dat
...\....\........\_primary.vhd
...\....\........\verilog.asm
...\....\........_testbench\_primary.dat
...\....\..................\_primary.vhd
...\....\..................\verilog.asm
...\....\......en\_primary.dat
...\....\........\_primary.vhd
...\....\........\verilog.asm
...\....\........_de\_primary.dat
...\....\...........\_primary.vhd
...\....\...........\verilog.asm
...\....\.........testbench\_primary.dat
...\....\..................\_primary.vhd
...\....\..................\verilog.asm
...\....\manch_de
...\....\manch_de_testbench
...\....\manch_en
...\....\manch_en_de
...\....\manch_en_testbench
...\chart
...\wave
...\work
4.2
...\manch_de.v
...\manch_de_testbench.v
...\manch_en.rpt
...\manch_en.v
...\manch_en_de.cr.mti
...\manch_en_de.mpf
...\manch_en_de.v
...\manch_en_testbench.v
...\transcript
...\vsim.wlf
...\chart\Thumbs.db
...\.....\图4-5.bmp
...\.....\图4-7.bmp
...\wave\Thumbs.db
...\....\manch_de.bmp
...\....\manch_de_testbench.bmp
...\....\manch_en.bmp
...\....\manch_en_testbench.bmp
...\.ork\_info
...\....\manch_de\_primary.dat
...\....\........\_primary.vhd
...\....\........\verilog.asm
...\....\........_testbench\_primary.dat
...\....\..................\_primary.vhd
...\....\..................\verilog.asm
...\....\......en\_primary.dat
...\....\........\_primary.vhd
...\....\........\verilog.asm
...\....\........_de\_primary.dat
...\....\...........\_primary.vhd
...\....\...........\verilog.asm
...\....\.........testbench\_primary.dat
...\....\..................\_primary.vhd
...\....\..................\verilog.asm
...\....\manch_de
...\....\manch_de_testbench
...\....\manch_en
...\....\manch_en_de
...\....\manch_en_testbench
...\chart
...\wave
...\work
4.2