文件名称:xge_mac
介绍说明－－下载内容均来自于网络，请自行研究使用
10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-========================
10GE MAC Core
========================
------------------------
1. Directory Structure
------------------------
The directory structure for this project is shown below.
.
|-- doc - Documentation files
|
|-- rtl
| |-- include - Verilog defines and utils
| `-- verilog - Verilog source files for xge_mac
|
|-- sim
| |-- systemc - SystemC simulation directory
| `-- verilog - Verilog simulation directory
|
`-- tbench
|-- systemc - SystemC test-bench source files
`-- verilog - Verilog test-bench source files
------------------------
2. Simulation
------------------------
There are two simulation environments that can be used to validate the code.
The verilog simulation is very basic and meant for those who want to look
at how the MAC operates without going through the effort of setting up SystemC.
The SystemC environment is more sophisticated and covers
10GE MAC Core
========================
------------------------
1. Directory Structure
------------------------
The directory structure for this project is shown below.
.
|-- doc - Documentation files
|
|-- rtl
| |-- include - Verilog defines and utils
| `-- verilog - Verilog source files for xge_mac
|
|-- sim
| |-- systemc - SystemC simulation directory
| `-- verilog - Verilog simulation directory
|
`-- tbench
|-- systemc - SystemC test-bench source files
`-- verilog - Verilog test-bench source files
------------------------
2. Simulation
------------------------
There are two simulation environments that can be used to validate the code.
The verilog simulation is very basic and meant for those who want to look
at how the MAC operates without going through the effort of setting up SystemC.
The SystemC environment is more sophisticated and covers
(系统自动生成,下载前可以参看下载内容)
下载文件列表
xge_mac(verilog 源码)\tags\initial\doc\xge_mac_spec.odt
.....................\....\.......\README.TXT
.....................\....\.......\rtl\auto_verilog.sh
.....................\....\.......\...\custom.el
.....................\....\.......\...\include\CRC32_D64.v
.....................\....\.......\...\.......\CRC32_D8.v
.....................\....\.......\...\.......\defines.v
.....................\....\.......\...\.......\timescale.v
.....................\....\.......\...\.......\utils.v
.....................\....\.......\...\verilog\fault_sm.v
.....................\....\.......\...\.......\generic_fifo.v
.....................\....\.......\...\.......\generic_fifo_ctrl.v
.....................\....\.......\...\.......\generic_mem_medium.v
.....................\....\.......\...\.......\generic_mem_small.v
.....................\....\.......\...\.......\meta_sync.v
.....................\....\.......\...\.......\meta_sync_single.v
.....................\....\.......\...\.......\rx_data_fifo.v
.....................\....\.......\...\.......\rx_dequeue.v
.....................\....\.......\...\.......\rx_enqueue.v
.....................\....\.......\...\.......\rx_hold_fifo.v
.....................\....\.......\...\.......\sync_clk_core.v
.....................\....\.......\...\.......\sync_clk_wb.v
.....................\....\.......\...\.......\sync_clk_xgmii_tx.v
.....................\....\.......\...\.......\tx_data_fifo.v
.....................\....\.......\...\.......\tx_dequeue.v
.....................\....\.......\...\.......\tx_enqueue.v
.....................\....\.......\...\.......\tx_hold_fifo.v
.....................\....\.......\...\.......\wishbone_if.v
.....................\....\.......\...\.......\xge_mac.v
.....................\....\.......\sim\systemc\compile.sh
.....................\....\.......\...\.......\run.sh
.....................\....\.......\...\.......\sc.mk
.....................\....\.......\...\.......\verilator.cmd
.....................\....\.......\...\verilog\sim.do
.....................\....\.......\tbench\systemc\crc.cpp
.....................\....\.......\......\.......\crc.h
.....................\....\.......\......\.......\sc_cpu_if.cpp
.....................\....\.......\......\.......\sc_cpu_if.h
.....................\....\.......\......\.......\sc_main.cpp
.....................\....\.......\......\.......\sc_packet.cpp
.....................\....\.......\......\.......\sc_packet.h
.....................\....\.......\......\.......\sc_pkt_generator.cpp
.....................\....\.......\......\.......\sc_pkt_generator.h
.....................\....\.......\......\.......\sc_pkt_if.cpp
.....................\....\.......\......\.......\sc_pkt_if.h
.....................\....\.......\......\.......\sc_scoreboard.cpp
.....................\....\.......\......\.......\sc_scoreboard.h
.....................\....\.......\......\.......\sc_testbench.cpp
.....................\....\.......\......\.......\sc_testbench.h
.....................\....\.......\......\.......\sc_testcases.cpp
.....................\....\.......\......\.......\sc_testcases.h
.....................\....\.......\......\.......\sc_xgmii_if.cpp
.....................\....\.......\......\.......\sc_xgmii_if.h
.....................\....\.......\......\verilog\packets_tx.txt
.....................\....\.......\......\.......\tb_xge_mac.v
.....................\.runk\doc\drawings.odg
.....................\.....\...\xge_mac_spec.odt
.....................\.....\...\xge_mac_spec.pdf
.....................\.....\README.TXT
.....................\.....\rtl\auto_verilog.sh
.....................\.....\...\custom.el
.....................\.....\...\include\CRC32_D64.v
.....................\.....\...\.......\CRC32_D8.v
.....................\.....\...\.......\defines.v
.....................\.....\...\.......\timescale.v
.....................\.....\...\.......\utils.v
.....................\.....\...\verilog\fault_sm.v
.....................\.....\...\.......\generic_fifo.v
.....................\.....\...\.......\generic_fifo_ctrl.v
.....................\.....\...\.....
.....................\....\.......\README.TXT
.....................\....\.......\rtl\auto_verilog.sh
.....................\....\.......\...\custom.el
.....................\....\.......\...\include\CRC32_D64.v
.....................\....\.......\...\.......\CRC32_D8.v
.....................\....\.......\...\.......\defines.v
.....................\....\.......\...\.......\timescale.v
.....................\....\.......\...\.......\utils.v
.....................\....\.......\...\verilog\fault_sm.v
.....................\....\.......\...\.......\generic_fifo.v
.....................\....\.......\...\.......\generic_fifo_ctrl.v
.....................\....\.......\...\.......\generic_mem_medium.v
.....................\....\.......\...\.......\generic_mem_small.v
.....................\....\.......\...\.......\meta_sync.v
.....................\....\.......\...\.......\meta_sync_single.v
.....................\....\.......\...\.......\rx_data_fifo.v
.....................\....\.......\...\.......\rx_dequeue.v
.....................\....\.......\...\.......\rx_enqueue.v
.....................\....\.......\...\.......\rx_hold_fifo.v
.....................\....\.......\...\.......\sync_clk_core.v
.....................\....\.......\...\.......\sync_clk_wb.v
.....................\....\.......\...\.......\sync_clk_xgmii_tx.v
.....................\....\.......\...\.......\tx_data_fifo.v
.....................\....\.......\...\.......\tx_dequeue.v
.....................\....\.......\...\.......\tx_enqueue.v
.....................\....\.......\...\.......\tx_hold_fifo.v
.....................\....\.......\...\.......\wishbone_if.v
.....................\....\.......\...\.......\xge_mac.v
.....................\....\.......\sim\systemc\compile.sh
.....................\....\.......\...\.......\run.sh
.....................\....\.......\...\.......\sc.mk
.....................\....\.......\...\.......\verilator.cmd
.....................\....\.......\...\verilog\sim.do
.....................\....\.......\tbench\systemc\crc.cpp
.....................\....\.......\......\.......\crc.h
.....................\....\.......\......\.......\sc_cpu_if.cpp
.....................\....\.......\......\.......\sc_cpu_if.h
.....................\....\.......\......\.......\sc_main.cpp
.....................\....\.......\......\.......\sc_packet.cpp
.....................\....\.......\......\.......\sc_packet.h
.....................\....\.......\......\.......\sc_pkt_generator.cpp
.....................\....\.......\......\.......\sc_pkt_generator.h
.....................\....\.......\......\.......\sc_pkt_if.cpp
.....................\....\.......\......\.......\sc_pkt_if.h
.....................\....\.......\......\.......\sc_scoreboard.cpp
.....................\....\.......\......\.......\sc_scoreboard.h
.....................\....\.......\......\.......\sc_testbench.cpp
.....................\....\.......\......\.......\sc_testbench.h
.....................\....\.......\......\.......\sc_testcases.cpp
.....................\....\.......\......\.......\sc_testcases.h
.....................\....\.......\......\.......\sc_xgmii_if.cpp
.....................\....\.......\......\.......\sc_xgmii_if.h
.....................\....\.......\......\verilog\packets_tx.txt
.....................\....\.......\......\.......\tb_xge_mac.v
.....................\.runk\doc\drawings.odg
.....................\.....\...\xge_mac_spec.odt
.....................\.....\...\xge_mac_spec.pdf
.....................\.....\README.TXT
.....................\.....\rtl\auto_verilog.sh
.....................\.....\...\custom.el
.....................\.....\...\include\CRC32_D64.v
.....................\.....\...\.......\CRC32_D8.v
.....................\.....\...\.......\defines.v
.....................\.....\...\.......\timescale.v
.....................\.....\...\.......\utils.v
.....................\.....\...\verilog\fault_sm.v
.....................\.....\...\.......\generic_fifo.v
.....................\.....\...\.......\generic_fifo_ctrl.v
.....................\.....\...\.....