文件名称:verilog
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本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器,用Verilog编程首先实现4倍内插,再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the interpolation, and then taken to achieve five-fold.
相关搜索: software
radio
vhdl
code
interpolation
Interpolation
verilog
software
defined
radio
vhdl
抽取
内插
radio
vhdl
code
interpolation
Interpolation
verilog
software
defined
radio
vhdl
抽取
内插
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verilog.doc