Abstract—This paper proposes a new technique for face detection

and lip feature extraction. A real-time field-programmable

gate array (FPGA) implementation of the two proposed techniques

is also presented. Face detection is based on a naive Bayes classifier

that classifies an edge-extracted representation of an image. Using

edge representation significantly reduces the model’s size to only

5184 B, which is 2417 times smaller than a comparable statistical

modeling technique, while achieving an 86.6 correct detection

rate under various lighting conditions. Lip feature extraction uses

the contrast around the lip contour to extract the height and width

of the mouth, metrics that are useful for speech filtering. The

proposed FPGA system occupies only 15 050 logic cells, or about

six times less than a current comparable FPGA face detection

system.-Abstract—This paper proposes a new technique for face detection

and lip feature extraction. A real-time field-programmable

gate array (FPGA) implementation of the two proposed techniques

is also presented. Face detection is based on a naive Bayes classifier

that classifies an edge-extracted representation of an image. Using

edge representation significantly reduces the model’s size to only

5184 B, which is 2417 times smaller than a comparable statistical

modeling technique, while achieving an 86.6　correct detection

rate under various lighting conditions. Lip feature extraction uses

the contrast around the lip contour to extract the height and width

of the mouth, metrics that are useful for speech filtering. The

proposed FPGA system occupies only 15 050 logic cells, or about

six times less than a current comparable FPGA face detection

system.