文件名称:finalcoursework
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用VHDL代码写的模拟微处理器核程序，有计算模块和register file 等模块，并包含测试程序，调试程序 ACTIVE HDL-Simulation with the VHDL code is written in the microprocessor core procedures, such as computing modules, and register file module, and includes test program, the debugger ACTIVE HDL
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下载文件列表
finalcoursework
...............\finalcoursework
...............\finalcoursework.aws
...............\finalcoursework.wsw
...............\...............\0finalcoursework.mgf
...............\...............\1finalcoursework.mgf
...............\...............\3finalcoursework.mgf
...............\...............\bde.set
...............\...............\compilation.order
...............\...............\compile
...............\...............\compile.cfg
...............\...............\.......\contents.lib~finalcoursework
...............\...............\.......\finalcoursework.cmd
...............\...............\.......\finalcoursework.epr
...............\...............\.......\finalcoursework.erf
...............\...............\.......\sources.sth
...............\...............\Edfmap.ini
...............\...............\elaboration.log
...............\...............\finalcoursework.adf
...............\...............\finalcoursework.LIB
...............\...............\finalcoursework.wsp
...............\...............\log
...............\...............\...\console.log
...............\...............\projlib.cfg
...............\...............\slp
...............\...............\...\logs
...............\...............\src
...............\...............\...\alu.vhd
...............\...............\...\buffer.vhd
...............\...............\...\codetest.vhd
...............\...............\...\machine_connection.vhd
...............\...............\...\machine_instruction.vhd
...............\...............\...\rom.vhd
...............\...............\...\simulation.asdb
...............\...............\...\simulation.awc
...............\...............\...\testbench.vhd
...............\...............\...\wave.asdb
...............\...............\synthesis.order
...............\library.cfg
...............\finalcoursework
...............\finalcoursework.aws
...............\finalcoursework.wsw
...............\...............\0finalcoursework.mgf
...............\...............\1finalcoursework.mgf
...............\...............\3finalcoursework.mgf
...............\...............\bde.set
...............\...............\compilation.order
...............\...............\compile
...............\...............\compile.cfg
...............\...............\.......\contents.lib~finalcoursework
...............\...............\.......\finalcoursework.cmd
...............\...............\.......\finalcoursework.epr
...............\...............\.......\finalcoursework.erf
...............\...............\.......\sources.sth
...............\...............\Edfmap.ini
...............\...............\elaboration.log
...............\...............\finalcoursework.adf
...............\...............\finalcoursework.LIB
...............\...............\finalcoursework.wsp
...............\...............\log
...............\...............\...\console.log
...............\...............\projlib.cfg
...............\...............\slp
...............\...............\...\logs
...............\...............\src
...............\...............\...\alu.vhd
...............\...............\...\buffer.vhd
...............\...............\...\codetest.vhd
...............\...............\...\machine_connection.vhd
...............\...............\...\machine_instruction.vhd
...............\...............\...\rom.vhd
...............\...............\...\simulation.asdb
...............\...............\...\simulation.awc
...............\...............\...\testbench.vhd
...............\...............\...\wave.asdb
...............\...............\synthesis.order
...............\library.cfg