文件名称:TIC_TAC_game_gate_level
- 所属分类：
- 软件工程
- 资源属性：
- [Windows] [程序]
- 上传时间：
- 2012-11-26
- 文件大小：
- 258kb
- 下载次数：
- 0次
- 提 供 者：
- chen-c*******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
Tic Tac Game is a classic game. Two players are using code-named “0” and “1”, fill in rotation in TICTACTOEMIDLET. If any player gates the first straight line will win, and if nobody is successful then the tie
1. Top module name： TT (Filename: TT.v)
2. Input pins: IN_AtoI [8:0]
3. Output pins: OUT [1:0]
4. All of the input are 1-bit numbers.
5. You can only use the following gates in Table I, and it its neede to include ALL the delay information (Tplh, Tphl) in your design.
It can only use not, and, nand, or, nor, xor, xnor logic gates.
It can only use up to 4-input logic gates.-Tic Tac Game is a classic game. Two players are using code-named “0” and “1”, fill in rotation in TICTACTOEMIDLET. If any player gates the first straight line will win, and if nobody is successful then the tie
1. Top module name： TT (Filename: TT.v)
2. Input pins: IN_AtoI [8:0]
3. Output pins: OUT [1:0]
4. All of the input are 1-bit numbers.
5. You can only use the following gates in Table I, and it its neede to include ALL the delay information (Tplh, Tphl) in your design.
It can only use not, and, nand, or, nor, xor, xnor logic gates.
It can only use up to 4-input logic gates.
1. Top module name： TT (Filename: TT.v)
2. Input pins: IN_AtoI [8:0]
3. Output pins: OUT [1:0]
4. All of the input are 1-bit numbers.
5. You can only use the following gates in Table I, and it its neede to include ALL the delay information (Tplh, Tphl) in your design.
It can only use not, and, nand, or, nor, xor, xnor logic gates.
It can only use up to 4-input logic gates.-Tic Tac Game is a classic game. Two players are using code-named “0” and “1”, fill in rotation in TICTACTOEMIDLET. If any player gates the first straight line will win, and if nobody is successful then the tie
1. Top module name： TT (Filename: TT.v)
2. Input pins: IN_AtoI [8:0]
3. Output pins: OUT [1:0]
4. All of the input are 1-bit numbers.
5. You can only use the following gates in Table I, and it its neede to include ALL the delay information (Tplh, Tphl) in your design.
It can only use not, and, nand, or, nor, xor, xnor logic gates.
It can only use up to 4-input logic gates.
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下载文件列表
TIC_TAC_game_gate_level
.......................\01_run.f
.......................\GATE_LIB.v
.......................\INCA_libs
.......................\.........\.ncv.lock
.......................\.........\cds.lib
.......................\.........\hdl.var
.......................\.........\irun.lnx86.08.10.nc
.......................\.........\...................\.ncrun.lock
.......................\.........\...................\.ncv.lock
.......................\.........\...................\bind.lst.lnx86
.......................\.........\...................\cds.lib
.......................\.........\...................\cdsrun.lib
.......................\.........\...................\files.ts
.......................\.........\...................\hdl.var
.......................\.........\...................\hdlrun.var
.......................\.........\...................\ncelab.args
.......................\.........\...................\ncelab.env
.......................\.........\...................\ncelab.hrd
.......................\.........\...................\ncsim.args
.......................\.........\...................\ncsim.env
.......................\.........\...................\ncsim_restart.args
.......................\.........\...................\ncsim_restart.env
.......................\.........\...................\ncverilog.args
.......................\.........\...................\ncvlog.args
.......................\.........\...................\ncvlog.env
.......................\.........\...................\ncvlog.files
.......................\.........\...................\temp
.......................\.........\snap.lnx86.nc
.......................\.........\.............\.elab.args
.......................\.........\.............\.hard.args
.......................\.........\.............\.ncv.lock
.......................\.........\.............\bind.lst.lnx86
.......................\.........\.............\cds.lib
.......................\.........\.............\hdl.var
.......................\.........\snap.sun4v.nc
.......................\.........\.............\.elab.args
.......................\.........\.............\.hard.args
.......................\.........\.............\.ncv.lock
.......................\.........\.............\bind.lst.sun4v
.......................\.........\.............\cds.lib
.......................\.........\.............\hdl.var
.......................\.........\worklib
.......................\.........\.......\.cdsvmod
.......................\.........\.......\.inca.db.132.lnx86
.......................\.........\.......\.inca.db.164.lnx86
.......................\.........\.......\.inca.db.166.sun4v
.......................\.........\.......\cdsinfo.tag
.......................\.........\.......\inca.lnx86.132.pak
.......................\.........\.......\inca.lnx86.164.pak
.......................\.........\.......\inca.sun4v.166.pak
.......................\ncverilog.log
.......................\novas.rc
.......................\nWaveLog
.......................\........\novas.rc
.......................\........\nWave.cmd
.......................\........\nWave.cmd.bak
.......................\........\pes.bat
.......................\........\turbo.log
.......................\PATTERN.v
.......................\TESTBED.v
.......................\TT.fsdb
.......................\TT.v
.......................\01_run.f
.......................\GATE_LIB.v
.......................\INCA_libs
.......................\.........\.ncv.lock
.......................\.........\cds.lib
.......................\.........\hdl.var
.......................\.........\irun.lnx86.08.10.nc
.......................\.........\...................\.ncrun.lock
.......................\.........\...................\.ncv.lock
.......................\.........\...................\bind.lst.lnx86
.......................\.........\...................\cds.lib
.......................\.........\...................\cdsrun.lib
.......................\.........\...................\files.ts
.......................\.........\...................\hdl.var
.......................\.........\...................\hdlrun.var
.......................\.........\...................\ncelab.args
.......................\.........\...................\ncelab.env
.......................\.........\...................\ncelab.hrd
.......................\.........\...................\ncsim.args
.......................\.........\...................\ncsim.env
.......................\.........\...................\ncsim_restart.args
.......................\.........\...................\ncsim_restart.env
.......................\.........\...................\ncverilog.args
.......................\.........\...................\ncvlog.args
.......................\.........\...................\ncvlog.env
.......................\.........\...................\ncvlog.files
.......................\.........\...................\temp
.......................\.........\snap.lnx86.nc
.......................\.........\.............\.elab.args
.......................\.........\.............\.hard.args
.......................\.........\.............\.ncv.lock
.......................\.........\.............\bind.lst.lnx86
.......................\.........\.............\cds.lib
.......................\.........\.............\hdl.var
.......................\.........\snap.sun4v.nc
.......................\.........\.............\.elab.args
.......................\.........\.............\.hard.args
.......................\.........\.............\.ncv.lock
.......................\.........\.............\bind.lst.sun4v
.......................\.........\.............\cds.lib
.......................\.........\.............\hdl.var
.......................\.........\worklib
.......................\.........\.......\.cdsvmod
.......................\.........\.......\.inca.db.132.lnx86
.......................\.........\.......\.inca.db.164.lnx86
.......................\.........\.......\.inca.db.166.sun4v
.......................\.........\.......\cdsinfo.tag
.......................\.........\.......\inca.lnx86.132.pak
.......................\.........\.......\inca.lnx86.164.pak
.......................\.........\.......\inca.sun4v.166.pak
.......................\ncverilog.log
.......................\novas.rc
.......................\nWaveLog
.......................\........\novas.rc
.......................\........\nWave.cmd
.......................\........\nWave.cmd.bak
.......................\........\pes.bat
.......................\........\turbo.log
.......................\PATTERN.v
.......................\TESTBED.v
.......................\TT.fsdb
.......................\TT.v