文件名称:TemperatureMonitor_lab

  • 所属分类:
  • 其他小程序
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.82mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 王*
  • 相关连接:
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实现温度的实时的检测,使用Verilog语言,适用于actel公司的FPGA-To achieve real-time temperature detection, the use of Verilog language, the company' s FPGA for actel
相关搜索: fpga
temperature
vhdl

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下载文件列表

TemperatureMonitor_lab

......................\component

......................\constraint

......................\coreconsole

......................\designer

......................\........\impl1

......................\........\.....\simulation

......................\........\.....\TemperatureMonitor_top.dtf

......................\hdl

......................\phy_synthesis

......................\simulation

......................\smartgen

......................\........\analog

......................\........\common

......................\........\......\verilog

......................\........\flashmem

......................\........\........\input_memfiles

......................\........\PLL1

......................\stimulus

......................\synthesis

......................\.........\syntmp

......................\viewdraw

......................\........\sch

......................\........\sym

......................\........\vf

......................\........\wir

......................\constraint\TemperatureMonitor_top.pdc

......................\..........\TemperatureMonitor_top_1.pdc

......................\..........\TemperatureMonitor_top_2.pdc

......................\..........\TemperatureMonitor_top_sdc.sdc

......................\designer\impl1\designer.log

......................\........\.....\designer_genhdl.log

......................\........\.....\TemperatureMonitor_top.adb

......................\........\.....\.......................dtf\verify.log

......................\........\.....\TemperatureMonitor_top.ide_des

......................\........\.....\TemperatureMonitor_top.pdb

......................\........\.....\TemperatureMonitor_top.pdb.depends

......................\........\.....\TemperatureMonitor_top.stp

......................\........\.....\TemperatureMonitor_top.tcl

......................\........\.....\TemperatureMonitor_top_ba.sdf

......................\........\.....\TemperatureMonitor_top_ba.v

......................\hdl\hdlsynchk.tcl

......................\...\TemperatureMonitor_top.v

......................\simulation\analog_acm_ram_R0C0.mem

......................\..........\analog_assc_ram_R0C0.mem

......................\..........\analog_smev_ram_R0C0.mem

......................\..........\analog_smtr_ram_R0C0.mem

......................\..........\flashmem.mem

......................\..........\meminit.dat

......................\..........\modelsim.ini

......................\..........\modelsim.ini.sav

......................\.martgen\analog\analog.cfg

......................\........\......\analog.cxf

......................\........\......\analog.gen

......................\........\......\analog.log

......................\........\......\analog.ncf

......................\........\......\analog.v

......................\........\......\analog_acm.mem

......................\........\......\analog_acm_ram.hex

......................\........\......\analog_acm_ram_R0C0.mem

......................\........\......\analog_assc.mem

......................\........\......\analog_assc_ram.hex

......................\........\......\analog_assc_ram.v

......................\........\......\analog_assc_ram_R0C0.mem

......................\........\......\analog_assc_wrapper.v

......................\........\......\analog_smev.mem

......................\........\......\analog_smev_ram.hex

......................\........\......\analog_smev_ram.v

......................\........\......\analog_smev_ram_R0C0.mem

......................\........\......\analog_smev_wrapper.v

......................\........\......\analog_smtr.mem

......................\........\......\analog_smtr_ram.hex

......................\........\......\analog_smtr_ram.v

......................\........\......\analog_smtr_ram_R0C0.mem

......................\........\......\analog_smtr_wrapper.v

......................\........\analog_work.ixf

......................\........\common\commonFileInventory.xml

......................\........\......\verilog\assc.v

......................\........\......\.......\initcfg.v

......................\........\......\....

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