文件名称:VerilogHDL1-9
介绍说明－－下载内容均来自于网络，请自行研究使用
包含了许多实用的Verilog模块的代码-it includes many source code written in Verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Chapter-1\adder\adder.cr.mti
.........\.....\adder.mpf
.........\.....\adder.v
.........\.....\adder_testbench.do
.........\.....\adder_testbench.v
.........\.....\chart\Thumbs.db
.........\.....\.....\图1-3.bmp
.........\.....\.....\图1-4.bmp
.........\.....\.....\图1-5.bmp
.........\.....\.....\图1-6.bmp
.........\.....\.....\图1-7.bmp
.........\.....\.....\图1-8.bmp
.........\.....\transcript
.........\.....\vsim.wlf
.........\.....\work\adder\transcript
.........\.....\....\.....\verilog.txt.asm
.........\.....\....\.....\_primary.dat
.........\.....\....\.....\_primary.vhd
.........\.....\....\....._testbench\verilog.asm
.........\.....\....\...............\_primary.dat
.........\.....\....\...............\_primary.vhd
.........\.....\....\_info
........2\2.1\adder
.........\...\adder.cr.mti
.........\...\adder.mpf
.........\...\adder.v
.........\...\adder_testbench.v
.........\...\chart\Thumbs.db
.........\...\.....\图2-2.bmp
.........\...\.....\表2-1.bmp
.........\...\transcript
.........\...\vsim.wlf
.........\...\wave\adder.bmp
.........\...\....\adder_testbench.bmp
.........\...\....\Thumbs.db
.........\...\.ork\adder\verilog.asm
.........\...\....\.....\_primary.dat
.........\...\....\.....\_primary.vhd
.........\...\....\....._testbench\verilog.asm
.........\...\....\...............\_primary.dat
.........\...\....\...............\_primary.vhd
.........\...\....\_info
.........\..2\chart\Thumbs.db
.........\...\.....\图2-4.bmp
.........\...\.....\表2-2.bmp
.........\...\full_add.cr.mti
.........\...\full_add.mpf
.........\...\full_add.v
.........\...\full_add_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\wave\full_add.bmp
.........\...\....\full_add_testbench.bmp
.........\...\....\Thumbs.db
.........\...\.ork\full_add\verilog.asm
.........\...\....\........\_primary.dat
.........\...\....\........\_primary.vhd
.........\...\....\........_testbench\verilog.asm
.........\...\....\..................\_primary.dat
.........\...\....\..................\_primary.vhd
.........\...\....\_info
.........\..3\adder4.cr.mti
.........\...\adder4.mpf
.........\...\adder4.v
.........\...\adder4_testbench.v
.........\...\chart\Thumbs.db
.........\...\.....\图2-7.bmp
.........\...\transcript
.........\...\vsim.wlf
.........\...\wave\adder4.bmp
.........\...\....\adder4_testbench.bmp
.........\...\....\Thumbs.db
.........\...\.ork\adder4\verilog.asm
.........\...\....\......\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\......_testbench\verilog.asm
.........\...\....\................\_primary.dat
.........\...\....\................\_primary.vhd
.........\...\....\_info
.........\..4\chart\Thumbs.db
.........\...\.....\图2-10.bmp
.........\...\coun4_testbench.v
.........\...\count4.cr.mti
.........\...\count4.mpf
.........\...\count4.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\wave\coun4.bmp
.........\...\....\coun4_testbench.bmp
.........\...\....\Thumbs.db
.........\...\.ork\coun4_testbench\verilog.asm
.........\...\....\...............\_primary.dat
.........\...\....\...............\_primary.vhd
.........\...\....\....t4\verilog.asm
.........\...\....\......\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\_info
.........\..5\chart\Thumbs.db
.........\...\.....\图2-12.bmp
.........\...\.....\表2-3.bmp
.........\.....\adder.mpf
.........\.....\adder.v
.........\.....\adder_testbench.do
.........\.....\adder_testbench.v
.........\.....\chart\Thumbs.db
.........\.....\.....\图1-3.bmp
.........\.....\.....\图1-4.bmp
.........\.....\.....\图1-5.bmp
.........\.....\.....\图1-6.bmp
.........\.....\.....\图1-7.bmp
.........\.....\.....\图1-8.bmp
.........\.....\transcript
.........\.....\vsim.wlf
.........\.....\work\adder\transcript
.........\.....\....\.....\verilog.txt.asm
.........\.....\....\.....\_primary.dat
.........\.....\....\.....\_primary.vhd
.........\.....\....\....._testbench\verilog.asm
.........\.....\....\...............\_primary.dat
.........\.....\....\...............\_primary.vhd
.........\.....\....\_info
........2\2.1\adder
.........\...\adder.cr.mti
.........\...\adder.mpf
.........\...\adder.v
.........\...\adder_testbench.v
.........\...\chart\Thumbs.db
.........\...\.....\图2-2.bmp
.........\...\.....\表2-1.bmp
.........\...\transcript
.........\...\vsim.wlf
.........\...\wave\adder.bmp
.........\...\....\adder_testbench.bmp
.........\...\....\Thumbs.db
.........\...\.ork\adder\verilog.asm
.........\...\....\.....\_primary.dat
.........\...\....\.....\_primary.vhd
.........\...\....\....._testbench\verilog.asm
.........\...\....\...............\_primary.dat
.........\...\....\...............\_primary.vhd
.........\...\....\_info
.........\..2\chart\Thumbs.db
.........\...\.....\图2-4.bmp
.........\...\.....\表2-2.bmp
.........\...\full_add.cr.mti
.........\...\full_add.mpf
.........\...\full_add.v
.........\...\full_add_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\wave\full_add.bmp
.........\...\....\full_add_testbench.bmp
.........\...\....\Thumbs.db
.........\...\.ork\full_add\verilog.asm
.........\...\....\........\_primary.dat
.........\...\....\........\_primary.vhd
.........\...\....\........_testbench\verilog.asm
.........\...\....\..................\_primary.dat
.........\...\....\..................\_primary.vhd
.........\...\....\_info
.........\..3\adder4.cr.mti
.........\...\adder4.mpf
.........\...\adder4.v
.........\...\adder4_testbench.v
.........\...\chart\Thumbs.db
.........\...\.....\图2-7.bmp
.........\...\transcript
.........\...\vsim.wlf
.........\...\wave\adder4.bmp
.........\...\....\adder4_testbench.bmp
.........\...\....\Thumbs.db
.........\...\.ork\adder4\verilog.asm
.........\...\....\......\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\......_testbench\verilog.asm
.........\...\....\................\_primary.dat
.........\...\....\................\_primary.vhd
.........\...\....\_info
.........\..4\chart\Thumbs.db
.........\...\.....\图2-10.bmp
.........\...\coun4_testbench.v
.........\...\count4.cr.mti
.........\...\count4.mpf
.........\...\count4.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\wave\coun4.bmp
.........\...\....\coun4_testbench.bmp
.........\...\....\Thumbs.db
.........\...\.ork\coun4_testbench\verilog.asm
.........\...\....\...............\_primary.dat
.........\...\....\...............\_primary.vhd
.........\...\....\....t4\verilog.asm
.........\...\....\......\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\_info
.........\..5\chart\Thumbs.db
.........\...\.....\图2-12.bmp
.........\...\.....\表2-3.bmp