文件名称:vhdl
介绍说明－－下载内容均来自于网络，请自行研究使用
基于FPGA的I2C总线模拟，采用verilog HDL语言编写-I2C-bus FPGA-based simulation using verilog HDL language
(系统自动生成,下载前可以参看下载内容)
下载文件列表
vhdl\I2C.VHD
....\i2c_master_bit_ctrl.vhd
....\i2c_master_byte_ctrl.vhd
....\i2c_master_top.vhd
....\tst_ds1621.vhd
....\wishbone_i2c_master.vhd
vhdl
....\i2c_master_bit_ctrl.vhd
....\i2c_master_byte_ctrl.vhd
....\i2c_master_top.vhd
....\tst_ds1621.vhd
....\wishbone_i2c_master.vhd
vhdl