文件名称:pwm_VerilogHDLV1.1
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本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX ＰＬＵＳ ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
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下载文件列表
压缩包 : 103244846pwm_veriloghdlv1.1.rar 列表 pwm_VerilogHDLV1.1\filter(1).cnf pwm_VerilogHDLV1.1\filter(10).cnf pwm_VerilogHDLV1.1\filter(11).cnf pwm_VerilogHDLV1.1\filter(2).cnf pwm_VerilogHDLV1.1\filter(3).cnf pwm_VerilogHDLV1.1\filter(4).cnf pwm_VerilogHDLV1.1\filter(5).cnf pwm_VerilogHDLV1.1\filter(6).cnf pwm_VerilogHDLV1.1\filter(7).cnf pwm_VerilogHDLV1.1\filter(8).cnf pwm_VerilogHDLV1.1\filter(9).cnf pwm_VerilogHDLV1.1\filter.acf pwm_VerilogHDLV1.1\filter.cnf pwm_VerilogHDLV1.1\filter.fit pwm_VerilogHDLV1.1\filter.hif pwm_VerilogHDLV1.1\filter.jam pwm_VerilogHDLV1.1\filter.jbc pwm_VerilogHDLV1.1\filter.mmf pwm_VerilogHDLV1.1\filter.ndb pwm_VerilogHDLV1.1\filter.pin pwm_VerilogHDLV1.1\filter.pof pwm_VerilogHDLV1.1\filter.rpt pwm_VerilogHDLV1.1\filter.scf pwm_VerilogHDLV1.1\filter.snf pwm_VerilogHDLV1.1\filter.v pwm_VerilogHDLV1.1\LIB.DLS pwm_VerilogHDLV1.1\protect(1).cnf pwm_VerilogHDLV1.1\protect(10).cnf pwm_VerilogHDLV1.1\protect(11).cnf pwm_VerilogHDLV1.1\protect(12).cnf pwm_VerilogHDLV1.1\protect(13).cnf pwm_VerilogHDLV1.1\protect(2).cnf pwm_VerilogHDLV1.1\protect(3).cnf pwm_VerilogHDLV1.1\protect(4).cnf pwm_VerilogHDLV1.1\protect(5).cnf pwm_VerilogHDLV1.1\protect(6).cnf pwm_VerilogHDLV1.1\protect(7).cnf pwm_VerilogHDLV1.1\protect(8).cnf pwm_VerilogHDLV1.1\protect(9).cnf pwm_VerilogHDLV1.1\protect.acf pwm_VerilogHDLV1.1\protect.cnf pwm_VerilogHDLV1.1\protect.fit pwm_VerilogHDLV1.1\protect.hif pwm_VerilogHDLV1.1\protect.jam pwm_VerilogHDLV1.1\protect.jbc pwm_VerilogHDLV1.1\protect.mmf pwm_VerilogHDLV1.1\protect.ndb pwm_VerilogHDLV1.1\protect.pin pwm_VerilogHDLV1.1\protect.pof pwm_VerilogHDLV1.1\protect.rpt pwm_VerilogHDLV1.1\protect.scf pwm_VerilogHDLV1.1\protect.snf pwm_VerilogHDLV1.1\protect.v pwm_VerilogHDLV1.1\pwm(10).cnf pwm_VerilogHDLV1.1\pwm(11).cnf pwm_VerilogHDLV1.1\pwm(12).cnf pwm_VerilogHDLV1.1\pwm(13).cnf pwm_VerilogHDLV1.1\pwm(14).cnf pwm_VerilogHDLV1.1\pwm(15).cnf pwm_VerilogHDLV1.1\pwm(16).cnf pwm_VerilogHDLV1.1\pwm(17).cnf pwm_VerilogHDLV1.1\pwm(18).cnf pwm_VerilogHDLV1.1\pwm(19).cnf pwm_VerilogHDLV1.1\pwm(20).cnf pwm_VerilogHDLV1.1\pwm(21).cnf pwm_VerilogHDLV1.1\pwm(22).cnf pwm_VerilogHDLV1.1\pwm(23).cnf pwm_VerilogHDLV1.1\pwm(24).cnf pwm_VerilogHDLV1.1\pwm(25).cnf pwm_VerilogHDLV1.1\pwm(26).cnf pwm_VerilogHDLV1.1\pwm(27).cnf pwm_VerilogHDLV1.1\pwm(28).cnf pwm_VerilogHDLV1.1\pwm(29).cnf pwm_VerilogHDLV1.1\pwm(30).cnf pwm_VerilogHDLV1.1\pwm(31).cnf pwm_VerilogHDLV1.1\pwm(32).cnf pwm_VerilogHDLV1.1\pwm(33).cnf pwm_VerilogHDLV1.1\pwm(34).cnf pwm_VerilogHDLV1.1\pwm(35).cnf pwm_VerilogHDLV1.1\pwm(36).cnf pwm_VerilogHDLV1.1\pwm(37).cnf pwm_VerilogHDLV1.1\pwm(38).cnf pwm_VerilogHDLV1.1\pwm(39).cnf pwm_VerilogHDLV1.1\pwm(4).cnf pwm_VerilogHDLV1.1\pwm(40).cnf pwm_VerilogHDLV1.1\pwm(6).cnf pwm_VerilogHDLV1.1\pwm(8).cnf pwm_VerilogHDLV1.1\pwm(9).cnf pwm_VerilogHDLV1.1\pwm.acf pwm_VerilogHDLV1.1\pwm.cnf pwm_VerilogHDLV1.1\pwm.fit pwm_VerilogHDLV1.1\pwm.hif pwm_VerilogHDLV1.1\pwm.jam pwm_VerilogHDLV1.1\pwm.jbc pwm_VerilogHDLV1.1\pwm.mmf pwm_VerilogHDLV1.1\pwm.ndb pwm_VerilogHDLV1.1\pwm.pin pwm_VerilogHDLV1.1\pwm.pof pwm_VerilogHDLV1.1\pwm.rpt pwm_VerilogHDLV1.1\pwm.scf pwm_VerilogHDLV1.1\pwm.snf pwm_VerilogHDLV1.1\pwm.v pwm_VerilogHDLV1.1\U1209224.DLS pwm_VerilogHDLV1.1\U2689902.DLS pwm_VerilogHDLV1.1\U9143042.DLS pwm_VerilogHDLV1.1