文件名称:gpio
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
一个可综合的verilog描述的GPIO代码。-A GPIO design in verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
gpio
....\bench
....\.....\CVS
....\.....\...\Entries
....\.....\...\Repository
....\.....\...\Root
....\.....\verilog
....\.....\.......\clkrst.v
....\.....\.......\CVS
....\.....\.......\...\Entries
....\.....\.......\...\Repository
....\.....\.......\...\Root
....\.....\.......\gpio_mon.v
....\.....\.......\gpio_testbench.v
....\.....\.......\tb_defines.v
....\.....\.......\tb_tasks.v
....\.....\.......\timescale.v
....\.....\.......\wb_master.v
....\.....\VHDL
....\.....\....\CVS
....\.....\....\...\Entries
....\.....\....\...\Repository
....\.....\....\...\Root
....\CVS
....\...\Entries
....\...\Repository
....\...\Root
....\doc
....\...\CVS
....\...\...\Entries
....\...\...\Repository
....\...\...\Root
....\...\gpio_spec.pdf
....\...\src
....\...\...\CVS
....\...\...\...\Entries
....\...\...\...\Repository
....\...\...\...\Root
....\...\...\gpio_spec.doc
....\fv
....\..\CVS
....\..\...\Entries
....\..\...\Repository
....\..\...\Root
....\gpio_spec.pdf
....\lint
....\....\bin
....\....\...\CVS
....\....\...\...\Entries
....\....\...\...\Repository
....\....\...\...\Root
....\....\CVS
....\....\...\Entries
....\....\...\Repository
....\....\...\Root
....\....\log
....\....\...\CVS
....\....\...\...\Entries
....\....\...\...\Repository
....\....\...\...\Root
....\....\out
....\....\...\CVS
....\....\...\...\Entries
....\....\...\...\Repository
....\....\...\...\Root
....\....\run
....\....\...\CVS
....\....\...\...\Entries
....\....\...\...\Repository
....\....\...\...\Root
....\rtl
....\...\CVS
....\...\...\Entries
....\...\...\Repository
....\...\...\Root
....\...\verilog
....\...\.......\CVS
....\...\.......\...\Entries
....\...\.......\...\Repository
....\...\.......\...\Root
....\...\.......\gpio_defines.v
....\...\.......\gpio_top.v
....\...\VHDL
....\...\....\CVS
....\...\....\...\Entries
....\...\....\...\Repository
....\...\....\...\Root
....\sim
....\...\CVS
....\...\...\Entries
....\...\...\Repository
....\...\...\Root
....\...\gate_sim
....\...\........\bin
....\...\........\...\CVS
....\...\........\...\...\Entries
....\...\........\...\...\Repository
....\...\........\...\...\Root
....\...\........\CVS
....\...\........\...\Entries
....\bench
....\.....\CVS
....\.....\...\Entries
....\.....\...\Repository
....\.....\...\Root
....\.....\verilog
....\.....\.......\clkrst.v
....\.....\.......\CVS
....\.....\.......\...\Entries
....\.....\.......\...\Repository
....\.....\.......\...\Root
....\.....\.......\gpio_mon.v
....\.....\.......\gpio_testbench.v
....\.....\.......\tb_defines.v
....\.....\.......\tb_tasks.v
....\.....\.......\timescale.v
....\.....\.......\wb_master.v
....\.....\VHDL
....\.....\....\CVS
....\.....\....\...\Entries
....\.....\....\...\Repository
....\.....\....\...\Root
....\CVS
....\...\Entries
....\...\Repository
....\...\Root
....\doc
....\...\CVS
....\...\...\Entries
....\...\...\Repository
....\...\...\Root
....\...\gpio_spec.pdf
....\...\src
....\...\...\CVS
....\...\...\...\Entries
....\...\...\...\Repository
....\...\...\...\Root
....\...\...\gpio_spec.doc
....\fv
....\..\CVS
....\..\...\Entries
....\..\...\Repository
....\..\...\Root
....\gpio_spec.pdf
....\lint
....\....\bin
....\....\...\CVS
....\....\...\...\Entries
....\....\...\...\Repository
....\....\...\...\Root
....\....\CVS
....\....\...\Entries
....\....\...\Repository
....\....\...\Root
....\....\log
....\....\...\CVS
....\....\...\...\Entries
....\....\...\...\Repository
....\....\...\...\Root
....\....\out
....\....\...\CVS
....\....\...\...\Entries
....\....\...\...\Repository
....\....\...\...\Root
....\....\run
....\....\...\CVS
....\....\...\...\Entries
....\....\...\...\Repository
....\....\...\...\Root
....\rtl
....\...\CVS
....\...\...\Entries
....\...\...\Repository
....\...\...\Root
....\...\verilog
....\...\.......\CVS
....\...\.......\...\Entries
....\...\.......\...\Repository
....\...\.......\...\Root
....\...\.......\gpio_defines.v
....\...\.......\gpio_top.v
....\...\VHDL
....\...\....\CVS
....\...\....\...\Entries
....\...\....\...\Repository
....\...\....\...\Root
....\sim
....\...\CVS
....\...\...\Entries
....\...\...\Repository
....\...\...\Root
....\...\gate_sim
....\...\........\bin
....\...\........\...\CVS
....\...\........\...\...\Entries
....\...\........\...\...\Repository
....\...\........\...\...\Root
....\...\........\CVS
....\...\........\...\Entries