文件名称:VHDL_100_1
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [Text]
- 上传时间：
- 2012-11-26
- 文件大小：
- 333kb
- 下载次数：
- 0次
- 提 供 者：
- z**
- 相关连接：
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- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
第43例 四位移位寄存器
第44例 寄存／计数器
第45例 顺序过程调用
第46例 VHDL中generic缺省值的使用
第47例 无输入元件的模拟
第48例 测试激励向量的编写
第49例 delta延迟例释
第50例 惯性延迟分析
第51例 传输延迟驱动优先
第52例 多倍（次）分频器
第53例 三位计数器与测试平台
第54例 分秒计数显示器的行为描述6
第55例 地址计数器
第56例 指令预读计数器
第57例 加.c减.c乘指令的译码和操作
第58例 2－4译码器结构描述
第59例 2－4译码器行为描述
第60例 转换函数在元件例示中的应用
第61例 基于同一基类型的两分辨类型的赋值相容问题
第62例 最大公约数的计算
第63例 最大公约数七段显示器编码
第64例 交通灯控制器
第65例 空调系统有限状态自动机
第66例 FIR滤波器
第67例 五阶椭圆滤波器
第68例 闹钟系统的控制
第69例 闹钟系统的译码
第70例 闹钟系统的移位寄存器
第71例 闹钟系统的闹钟寄存器和时间计数器
第72例 闹钟系统的显示驱动器
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VHDL语言100例(普通下载)
.......................\100vhdl例子
.......................\...........\10_function
.......................\...........\...........\10_bit_to_int.vhd
.......................\...........\...........\README.TXT
.......................\...........\11_wiredor
.......................\...........\..........\11_wiredor.vhd
.......................\...........\..........\README.TXT
.......................\...........\12_convert
.......................\...........\..........\12_convert.vhd
.......................\...........\..........\README.TXT
.......................\...........\13_SHL
.......................\...........\......\13_SHL.VHD
.......................\...........\......\README.TXT
.......................\...........\14_MVL7_functions
.......................\...........\.................\14_MVL7_functions.vhd
.......................\...........\.................\README.TXT
.......................\...........\15_MUX41
.......................\...........\........\15_MUX41.VHD
.......................\...........\........\15_MVL7_functions.vhd
.......................\...........\........\15_MVL7_syn_types.vhd
.......................\...........\........\15_test_vectors_mux41.vhd
.......................\...........\........\15_TYPES.VHD
.......................\...........\........\README.TXT
.......................\...........\16_MUX
.......................\...........\......\16_multiple_mux.vhd
.......................\...........\......\16_MVL7_functions.vhd
.......................\...........\......\16_test_vectors.vhd
.......................\...........\......\16_TYPES.VHD
.......................\...........\......\README.TXT
.......................\...........\......\TYPES.VHD
.......................\...........\17_parity
.......................\...........\.........\17_parity.vhd
.......................\...........\.........\17_test_bench.vhd
.......................\...........\.........\README.TXT
.......................\...........\18_LIB
.......................\...........\......\18_tech_lib.vhd
.......................\...........\......\18_test_lib.vhd
.......................\...........\......\README.TXT
.......................\...........\19_test_194
.......................\...........\...........\19_test_194.vhd
.......................\...........\1_ADDER
.......................\...........\.......\1_ADDER
.......................\...........\.......\.......\1_ADDER.exp
.......................\...........\.......\.......\files
.......................\...........\.......\.......\.....\L1.rpt
.......................\...........\.......\.......\.....\L2.rpt
.......................\...........\.......\.......\.....\L3.rpt
.......................\...........\.......\.......\workdirs
.......................\...........\.......\.......\........\aa
.......................\...........\.......\.......\........\..\ADDER.sim
.......................\...........\.......\.......\........\..\ADDER.syn
.......................\...........\.......\.......\........\..\Anal.info
.......................\...........\.......\.......\........\..\Anal.out
.......................\...........\.......\.......\........\WORK
.......................\...........\.......\.......\........\....\Anal.info
.......................\...........\.......\.......\........\....\Anal.out
.......................\...........\.......\.......\........\....\BIT_RTL_ADDER.sim
.......................\...........\.......\.......\........\....\BIT_RTL_ADDER.syn
.......................\...........\.......\1_adder.acf
.......................\...........\.......\1_adder.hif
.......................\...........\.......\1_adder.mmf
.......................\...........\.......\1_ADDER.VHD
.......................\...........\.......\bir_rtl_adder.acf
.......................\...........\.......\bir_rtl_adder.hif
.......................\...........\.......\bir_rtl_adder.mmf
.......................\...........\.......\bir_rtl_adder.tdf
.......................\...........\.......\bit_rtl_adder.acf
.......................\...........\.......\bit_rtl_adder.
.......................\100vhdl例子
.......................\...........\10_function
.......................\...........\...........\10_bit_to_int.vhd
.......................\...........\...........\README.TXT
.......................\...........\11_wiredor
.......................\...........\..........\11_wiredor.vhd
.......................\...........\..........\README.TXT
.......................\...........\12_convert
.......................\...........\..........\12_convert.vhd
.......................\...........\..........\README.TXT
.......................\...........\13_SHL
.......................\...........\......\13_SHL.VHD
.......................\...........\......\README.TXT
.......................\...........\14_MVL7_functions
.......................\...........\.................\14_MVL7_functions.vhd
.......................\...........\.................\README.TXT
.......................\...........\15_MUX41
.......................\...........\........\15_MUX41.VHD
.......................\...........\........\15_MVL7_functions.vhd
.......................\...........\........\15_MVL7_syn_types.vhd
.......................\...........\........\15_test_vectors_mux41.vhd
.......................\...........\........\15_TYPES.VHD
.......................\...........\........\README.TXT
.......................\...........\16_MUX
.......................\...........\......\16_multiple_mux.vhd
.......................\...........\......\16_MVL7_functions.vhd
.......................\...........\......\16_test_vectors.vhd
.......................\...........\......\16_TYPES.VHD
.......................\...........\......\README.TXT
.......................\...........\......\TYPES.VHD
.......................\...........\17_parity
.......................\...........\.........\17_parity.vhd
.......................\...........\.........\17_test_bench.vhd
.......................\...........\.........\README.TXT
.......................\...........\18_LIB
.......................\...........\......\18_tech_lib.vhd
.......................\...........\......\18_test_lib.vhd
.......................\...........\......\README.TXT
.......................\...........\19_test_194
.......................\...........\...........\19_test_194.vhd
.......................\...........\1_ADDER
.......................\...........\.......\1_ADDER
.......................\...........\.......\.......\1_ADDER.exp
.......................\...........\.......\.......\files
.......................\...........\.......\.......\.....\L1.rpt
.......................\...........\.......\.......\.....\L2.rpt
.......................\...........\.......\.......\.....\L3.rpt
.......................\...........\.......\.......\workdirs
.......................\...........\.......\.......\........\aa
.......................\...........\.......\.......\........\..\ADDER.sim
.......................\...........\.......\.......\........\..\ADDER.syn
.......................\...........\.......\.......\........\..\Anal.info
.......................\...........\.......\.......\........\..\Anal.out
.......................\...........\.......\.......\........\WORK
.......................\...........\.......\.......\........\....\Anal.info
.......................\...........\.......\.......\........\....\Anal.out
.......................\...........\.......\.......\........\....\BIT_RTL_ADDER.sim
.......................\...........\.......\.......\........\....\BIT_RTL_ADDER.syn
.......................\...........\.......\1_adder.acf
.......................\...........\.......\1_adder.hif
.......................\...........\.......\1_adder.mmf
.......................\...........\.......\1_ADDER.VHD
.......................\...........\.......\bir_rtl_adder.acf
.......................\...........\.......\bir_rtl_adder.hif
.......................\...........\.......\bir_rtl_adder.mmf
.......................\...........\.......\bir_rtl_adder.tdf
.......................\...........\.......\bit_rtl_adder.acf
.......................\...........\.......\bit_rtl_adder.