文件名称:S5_UART
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog编写的UART程序，是红色飓风EP1C6板子上面的程序-this is a UART project with verilog language,it is the programmer by the redlogic s EP1C6 board
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Doc
...\sscom.ini
...\sscom32.exe
...\UART控制器设计说明.doc
...\xapp341.pdf
func_sim
........\rcvr.v
........\transcript
........\txmit.v
........\txmit_tf.do
........\uart.cr.mti
........\uart.mpf
........\uart.v
........\uart_if.v
........\uart_tb.do
........\uart_tb.v
........\uart_tb_fixed.do
........\vish_stacktrace.vstf
........\vsim.wlf
........\wave.do
........\work
........\....\@u@a@r@t_tb
........\....\...........\verilog.asm
........\....\...........\_primary.dat
........\....\...........\_primary.vhd
........\....\rcvr
........\....\....\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\txmit
........\....\.....\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\uart
........\....\....\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\uart_if
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\_info
physical
........\altclklock0.bsf
........\altclklock0.v
........\altclklock0_bb.v
........\async_transmitter.bsf
........\cmp_state.ini
........\db
........\..\altsyncram_8tj.tdf
........\..\altsyncram_9un.tdf
........\..\altsyncram_g5q.tdf
........\..\altsyncram_s931.tdf
........\..\cntr_cs6.tdf
........\..\cntr_gs6.tdf
........\..\cntr_ub7.tdf
........\..\cntr_vt6.tdf
........\..\prev_cmp_uart_if.asm.qmsg
........\..\prev_cmp_uart_if.eda.qmsg
........\..\prev_cmp_uart_if.fit.qmsg
........\..\prev_cmp_uart_if.map.qmsg
........\..\prev_cmp_uart_if.qmsg
........\..\prev_cmp_uart_if.tan.qmsg
........\..\prev_cmp_vga.map.qmsg
........\..\prev_cmp_vga.qmsg
........\..\uart_if.asm.qmsg
........\..\uart_if.cbx.xml
........\..\uart_if.cmp.bpm
........\..\uart_if.cmp.cdb
........\..\uart_if.cmp.ecobp
........\..\uart_if.cmp.hdb
........\..\uart_if.cmp.logdb
........\..\uart_if.cmp.rdb
........\..\uart_if.cmp.tdb
........\..\uart_if.cmp0.ddb
........\..\uart_if.cmp_bb.cdb
........\..\uart_if.cmp_bb.hdb
........\..\uart_if.cmp_bb.logdb
........\..\uart_if.cmp_bb.rcf
........\..\uart_if.dbp
........\..\uart_if.db_info
........\..\uart_if.eco.cdb
........\..\uart_if.eda.qmsg
........\..\uart_if.fit.qmsg
........\..\uart_if.hier_info
........\..\uart_if.hif
........\..\uart_if.map.bpm
........\..\uart_if.map.cdb
........\..\uart_if.map.ecobp
........\..\uart_if.map.hdb
........\..\uart_if.map.logdb
........\..\uart_if.map.qmsg
........\..\uart_if.map_bb.cdb
........\..\uart_if.map_bb.hdb
........\..\uart_if.map_bb.logdb
........\..\uart_if.pre_map.cdb
........\..\uart_if.pre_map.hdb
........\..\uart_if.psp
........\..\uart_if.pss
........\..\uart_if.rtlv.hdb
...\sscom.ini
...\sscom32.exe
...\UART控制器设计说明.doc
...\xapp341.pdf
func_sim
........\rcvr.v
........\transcript
........\txmit.v
........\txmit_tf.do
........\uart.cr.mti
........\uart.mpf
........\uart.v
........\uart_if.v
........\uart_tb.do
........\uart_tb.v
........\uart_tb_fixed.do
........\vish_stacktrace.vstf
........\vsim.wlf
........\wave.do
........\work
........\....\@u@a@r@t_tb
........\....\...........\verilog.asm
........\....\...........\_primary.dat
........\....\...........\_primary.vhd
........\....\rcvr
........\....\....\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\txmit
........\....\.....\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\uart
........\....\....\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\uart_if
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\_info
physical
........\altclklock0.bsf
........\altclklock0.v
........\altclklock0_bb.v
........\async_transmitter.bsf
........\cmp_state.ini
........\db
........\..\altsyncram_8tj.tdf
........\..\altsyncram_9un.tdf
........\..\altsyncram_g5q.tdf
........\..\altsyncram_s931.tdf
........\..\cntr_cs6.tdf
........\..\cntr_gs6.tdf
........\..\cntr_ub7.tdf
........\..\cntr_vt6.tdf
........\..\prev_cmp_uart_if.asm.qmsg
........\..\prev_cmp_uart_if.eda.qmsg
........\..\prev_cmp_uart_if.fit.qmsg
........\..\prev_cmp_uart_if.map.qmsg
........\..\prev_cmp_uart_if.qmsg
........\..\prev_cmp_uart_if.tan.qmsg
........\..\prev_cmp_vga.map.qmsg
........\..\prev_cmp_vga.qmsg
........\..\uart_if.asm.qmsg
........\..\uart_if.cbx.xml
........\..\uart_if.cmp.bpm
........\..\uart_if.cmp.cdb
........\..\uart_if.cmp.ecobp
........\..\uart_if.cmp.hdb
........\..\uart_if.cmp.logdb
........\..\uart_if.cmp.rdb
........\..\uart_if.cmp.tdb
........\..\uart_if.cmp0.ddb
........\..\uart_if.cmp_bb.cdb
........\..\uart_if.cmp_bb.hdb
........\..\uart_if.cmp_bb.logdb
........\..\uart_if.cmp_bb.rcf
........\..\uart_if.dbp
........\..\uart_if.db_info
........\..\uart_if.eco.cdb
........\..\uart_if.eda.qmsg
........\..\uart_if.fit.qmsg
........\..\uart_if.hier_info
........\..\uart_if.hif
........\..\uart_if.map.bpm
........\..\uart_if.map.cdb
........\..\uart_if.map.ecobp
........\..\uart_if.map.hdb
........\..\uart_if.map.logdb
........\..\uart_if.map.qmsg
........\..\uart_if.map_bb.cdb
........\..\uart_if.map_bb.hdb
........\..\uart_if.map_bb.logdb
........\..\uart_if.pre_map.cdb
........\..\uart_if.pre_map.hdb
........\..\uart_if.psp
........\..\uart_if.pss
........\..\uart_if.rtlv.hdb