文件名称:chengxu(vhdl)
介绍说明－－下载内容均来自于网络，请自行研究使用
这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 119128637chengxu(vhdl).rar 列表 vhdl\uart_sent\top.qpf vhdl\uart_sent\top.qsf vhdl\uart_sent\fenpin_even.vhd vhdl\uart_sent\top.map.eqn vhdl\uart_sent\top.map.rpt vhdl\uart_sent\top.flow.rpt vhdl\uart_sent\top.map.summary vhdl\uart_sent\top.fit.eqn vhdl\uart_sent\top.pin vhdl\uart_sent\top.fit.rpt vhdl\uart_sent\top.fit.summary vhdl\uart_sent\top.sof vhdl\uart_sent\top.pof vhdl\uart_sent\top.asm.rpt vhdl\uart_sent\top.tan.summary vhdl\uart_sent\top.tan.rpt vhdl\uart_sent\top.done vhdl\uart_sent\fenpin_115200.bsf vhdl\uart_sent\sent.bsf vhdl\uart_sent\fenpin_115200.vhd vhdl\uart_sent\top.bdf vhdl\uart_sent\top.qws vhdl\uart_sent\cmp_state.ini vhdl\uart_sent\中电网新设计新应用.htm vhdl\uart_sent\sent.vhd vhdl\uart_sent\中电网新设计新应用.files\ECNet-logo.jpg vhdl\uart_sent\中电网新设计新应用.files\eng.gif vhdl\uart_sent\中电网新设计新应用.files\big5.gif vhdl\uart_sent\中电网新设计新应用.files\ni061012.gif vhdl\uart_sent\中电网新设计新应用.files\space.jpg vhdl\uart_sent\中电网新设计新应用.files\icbase-logo.gif vhdl\uart_sent\中电网新设计新应用.files\wdj.gif vhdl\uart_sent\中电网新设计新应用.files\maruwa-logo.gif vhdl\uart_sent\中电网新设计新应用.files\20-1.gif vhdl\uart_sent\中电网新设计新应用.files\20-2.gif vhdl\uart_sent\中电网新设计新应用.files\20-3.gif vhdl\uart_sent\中电网新设计新应用.files\20-4.gif vhdl\uart_sent\中电网新设计新应用.files\20-5.gif vhdl\uart_sent\中电网新设计新应用.files\banner-b.gif vhdl\uart_sent\中电网新设计新应用.files\l-b1.jpg vhdl\uart_sent\中电网新设计新应用.files\style.css vhdl\uart_sent\中电网新设计新应用.files\adfshow.htm vhdl\uart_sent\中电网新设计新应用.files\adfshow(1).htm vhdl\uart_sent\中电网新设计新应用.files\adfshow(2).htm vhdl\uart_sent\中电网新设计新应用.files\adfshow(3).htm vhdl\uart_sent\中电网新设计新应用.files\adlink.htm vhdl\uart_sent\中电网新设计新应用.files\Thumbs.db vhdl\uart_sent\中电网新设计新应用.files\adfshow(3).files\ons-banner.gif vhdl\uart_sent\中电网新设计新应用.files\adfshow(3).files\Thumbs.db vhdl\uart_sent\中电网新设计新应用.files\adfshow(3).files vhdl\uart_sent\中电网新设计新应用.files\adfshow(2).files\xcell23-167-061019.gif vhdl\uart_sent\中电网新设计新应用.files\adfshow(2).files\Thumbs.db vhdl\uart_sent\中电网新设计新应用.files\adfshow(2).files vhdl\uart_sent\中电网新设计新应用.files\adfshow(1).files\160-060929.gif vhdl\uart_sent\中电网新设计新应用.files\adfshow(1).files\Thumbs.db vhdl\uart_sent\中电网新设计新应用.files\adfshow(1).files vhdl\uart_sent\中电网新设计新应用.files\adfshow.files\ADI400-061025.gif vhdl\uart_sent\中电网新设计新应用.files\adfshow.files\Thumbs.db vhdl\uart_sent\中电网新设计新应用.files\adfshow.files vhdl\uart_sent\中电网新设计新应用.files vhdl\uart_sent\db\top.db_info vhdl\uart_sent\db\top.(2).cnf.cdb vhdl\uart_sent\db\top.cmp.rdb vhdl\uart_sent\db\top.(2).cnf.hdb vhdl\uart_sent\db\top.(1).cnf.cdb vhdl\uart_sent\db\top.sld_design_entry.sci vhdl\uart_sent\db\top.rtlv.hdb vhdl\uart_sent\db\top.map.qmsg vhdl\uart_sent\db\top.eco.cdb vhdl\uart_sent\db\top_cmp.qrpt vhdl\uart_sent\db\top.cbx.xml vhdl\uart_sent\db\top.hif vhdl\uart_sent\db\top.rtlv_sg_swap.cdb vhdl\uart_sent\db\top.(1).cnf.hdb vhdl\uart_sent\db\top.hier_info vhdl\uart_sent\db\top.pre_map.cdb vhdl\uart_sent\db\top.fit.qmsg vhdl\uart_sent\db\top.pre_map.hdb vhdl\uart_sent\db\top.rtlv_sg.cdb vhdl\uart_sent\db\top.map.hdb vhdl\uart_sent\db\top.sgdiff.hdb vhdl\uart_sent\db\top.psp vhdl\uart_sent\db\top.asm.qmsg vhdl\uart_sent\db\top.sld_design_entry_dsc.sci vhdl\uart_sent\db\top.syn_hier_info vhdl\uart_sent\db\top.map.cdb vhdl\uart_sent\db\top.tan.qmsg vhdl\uart_sent\db\top.sgdiff.cdb vhdl\uart_sent\db\top.cmp0.ddb vhdl\uart_sent\db\top.cmp.cdb vhdl\uart_sent\db\top.signalprobe.cdb vhdl\uart_sent\db\top.cmp.hdb vhdl\uart_sent\db\top.cmp.tdb vhdl\uart_sent\db\top.(0).cnf.cdb vhdl\uart_sent\db\top.(0).cnf.hdb vhdl\uart_sent\db vhdl\uart_sent vhdl\led\top.qpf vhdl\led\top.qsf vhdl\led\top.map.eqn vhdl\led\top.map.rpt vhdl\led\top.flow.rpt vhdl\led\top.map.summary vhdl\led\top.fit.eqn vhdl\led\top.pin vhdl\led\top.fit.rpt vhdl\led\top.fit.summary vhdl\led\top.sof vhdl\led\top.pof vhdl\led\top.asm.rpt vhdl\led\top.tan.summary vhdl\led\top.tan.rpt vhdl\led\top.eda.rpt vhdl\led\top.done vhdl\led\fenpin.bsf vhdl\led\control.bsf vhdl\led\top.qws vhdl\led\cmp_state.ini vhdl\led\top.bdf vhdl\led\top.cdf vhdl\led\undo_redo.txt vhdl\led\control.vhd vhdl\led\fenpin.vhd vhdl\led\db\top.db_info vhdl\led\db\top.cmp.rdb vhdl\led\db\top.tan.qmsg vhdl\led\db\top.(1).cnf.cdb vhdl\led\db\top.eco.cdb vhdl\led\db\top.(2).cnf.cdb vhdl\led\db\top.rtlv.hdb vhdl\led\db\top.eda.qmsg vhdl\led\db\top.sld_design_entry.sci vhdl\led\db\top.cbx.xml vhdl\led\db\top_cmp.qrpt vhdl\led\db\top.hif vhdl\led\db\top.fit.qmsg vhdl\led\db\top.(2).cnf.hdb vhdl\led\db\top.hier_info vhdl\led\db\top.map.qmsg vhdl\led\db\top.pre_map.hdb vhdl\led\db\top.(0).cnf.cdb vhdl\led\db\top.map.hdb vhdl\led\db\top.pre_map.cdb vhdl\led\db\top.(1).cnf.hdb vhdl\led\db\top.psp vhdl\led\db\top.map.cdb vhdl\led\db\top.cmp0.ddb vhdl\led\db\top.cmp.cdb vhdl\led\db\top.syn_hier_info vhdl\led\db\top.(0).cnf.hdb vhdl\led\db\top.rtlv_sg_swap.cdb vhdl\led\db\top.asm.qmsg vhdl\led\db\top.sgdiff.hdb vhdl\led\db\top.rtlv_sg.cdb vhdl\led\db\top.sgdiff.cdb vhdl\led\db\top.sld_design_entry_dsc.sci vhdl\led\db\top.signalprobe.cdb vhdl\led\db\top.cmp.hdb vhdl\led\db\top.cmp.tdb vhdl\led\db vhdl\led\simulation\modelsim\top_modelsim.xrf vhdl\led\simulation\modelsim\top.vo vhdl\led\simulation\modelsim\top_v.sdo vhdl\led\simulation\modelsim vhdl\led\simulation vhdl\led vhdl