文件名称:CPU_Architecture
- 所属分类：
- VHDL编程
- 资源属性：
- [Matlab] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 2.28mb
- 下载次数：
- 0次
- 提 供 者：
- Amit *****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks.
External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets.
The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
-Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks.
External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets.
The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets.
The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
-Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks.
External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets.
The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
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下载文件列表
Final_Project_Amit_Adoni_&_Tomer_Israel_CPU
...........................................\Do files
...........................................\........\2_words_crc.do
...........................................\........\2_words_crc2.do
...........................................\........\accelerator in the_system.do
...........................................\........\accelerator.do
...........................................\........\branch_logic(1).do
...........................................\........\branch_logic2.do
...........................................\........\cache.do
...........................................\........\cache_comp4.do
...........................................\........\calc_carry.do
...........................................\........\cell.do
...........................................\........\cell_vector.do
...........................................\........\cmos_mux.do
...........................................\........\comparator_1bit.do
...........................................\........\comparator_32bit(1).do
...........................................\........\comparator_4bit(1).do
...........................................\........\control_logic.do
...........................................\........\DFFS_wave.DO
...........................................\........\DFF_wave.do
...........................................\........\FA.do
...........................................\........\first_buffer.do
...........................................\........\first_stage.do
...........................................\........\first_stage_total.do
...........................................\........\hazard_logic.do
...........................................\........\multi_and.do
...........................................\........\multi_inverters.do
...........................................\........\multi_or.do
...........................................\........\multy_cmos_switch_test.do
...........................................\........\mux2(cmos).do
...........................................\........\mux2.do
...........................................\........\mux4.do
...........................................\........\P_G.do
...........................................\........\second_stage.do
...........................................\........\test_all.do
...........................................\........\test_all1.do
...........................................\........\the_system.do
...........................................\........\xor_2.do
...........................................\........\xor_3_input.do
...........................................\........\xor_4.do
...........................................\........\xor_6.do
...........................................\Matlab final project
...........................................\....................\add.m
...........................................\....................\addi.asv
...........................................\....................\addi.m
...........................................\....................\BinEncoder.asv
...........................................\....................\BinEncoder.m
...........................................\....................\BinEncoder1.m
...........................................\....................\bre.m
...........................................\....................\brg.m
...........................................\....................\brl.m
...........................................\....................\bubble_sort.txt
...........................................\....................\checksum.m
...........................................\....................\ConvertToInt.m
...........................................\....................\crc32.m
...........................................\....................\create_test_ram.m
...........................................\....................\culc_crc.asv
...........................................\....................\culc_crc.m
...........................................\....................\flush.m
............
...........................................\Do files
...........................................\........\2_words_crc.do
...........................................\........\2_words_crc2.do
...........................................\........\accelerator in the_system.do
...........................................\........\accelerator.do
...........................................\........\branch_logic(1).do
...........................................\........\branch_logic2.do
...........................................\........\cache.do
...........................................\........\cache_comp4.do
...........................................\........\calc_carry.do
...........................................\........\cell.do
...........................................\........\cell_vector.do
...........................................\........\cmos_mux.do
...........................................\........\comparator_1bit.do
...........................................\........\comparator_32bit(1).do
...........................................\........\comparator_4bit(1).do
...........................................\........\control_logic.do
...........................................\........\DFFS_wave.DO
...........................................\........\DFF_wave.do
...........................................\........\FA.do
...........................................\........\first_buffer.do
...........................................\........\first_stage.do
...........................................\........\first_stage_total.do
...........................................\........\hazard_logic.do
...........................................\........\multi_and.do
...........................................\........\multi_inverters.do
...........................................\........\multi_or.do
...........................................\........\multy_cmos_switch_test.do
...........................................\........\mux2(cmos).do
...........................................\........\mux2.do
...........................................\........\mux4.do
...........................................\........\P_G.do
...........................................\........\second_stage.do
...........................................\........\test_all.do
...........................................\........\test_all1.do
...........................................\........\the_system.do
...........................................\........\xor_2.do
...........................................\........\xor_3_input.do
...........................................\........\xor_4.do
...........................................\........\xor_6.do
...........................................\Matlab final project
...........................................\....................\add.m
...........................................\....................\addi.asv
...........................................\....................\addi.m
...........................................\....................\BinEncoder.asv
...........................................\....................\BinEncoder.m
...........................................\....................\BinEncoder1.m
...........................................\....................\bre.m
...........................................\....................\brg.m
...........................................\....................\brl.m
...........................................\....................\bubble_sort.txt
...........................................\....................\checksum.m
...........................................\....................\ConvertToInt.m
...........................................\....................\crc32.m
...........................................\....................\create_test_ram.m
...........................................\....................\culc_crc.asv
...........................................\....................\culc_crc.m
...........................................\....................\flush.m
............