文件名称:counter
- 所属分类：
- VHDL编程
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 128kb
- 下载次数：
- 0次
- 提 供 者：
- flyin******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
适用于FPGA Xilinx开发板的Counter程序，计数从0到9999，在板上用4位7段数码管显示，可实现双向计数。-Applicable to FPGA Xilinx development board of the Counter procedures, counting from 0 to 9999, in the board with four 7 digital display, enabling two-way counts.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
counter.doc
counter.v
counter.v.bak
counter.xml
counter_0to9999.v
counter_0to9999.v.bak
counter_divider.bak
counter_divider.v
counter_divider.v.bak
counter_tb.v
counter_tb.v.bak
modelsim.ini
sevenseg_display.v
sevenseg_display.v.bak
seven_control.v
seven_control.v.bak
transcript
vsim.wlf
work
....\counter
....\.......\verilog.asm
....\.......\_primary.dat
....\.......\_primary.vhd
....\counter_0to9999
....\...............\verilog.asm
....\...............\_primary.dat
....\...............\_primary.vhd
....\counter_divider
....\...............\verilog.asm
....\...............\_primary.dat
....\...............\_primary.vhd
....\counter_tb
....\..........\verilog.asm
....\..........\_primary.dat
....\..........\_primary.vhd
....\sevenseg_display
....\................\verilog.asm
....\................\_primary.dat
....\................\_primary.vhd
....\seven_contrl
....\............\verilog.asm
....\............\_primary.dat
....\............\_primary.vhd
....\_info
counter.v
counter.v.bak
counter.xml
counter_0to9999.v
counter_0to9999.v.bak
counter_divider.bak
counter_divider.v
counter_divider.v.bak
counter_tb.v
counter_tb.v.bak
modelsim.ini
sevenseg_display.v
sevenseg_display.v.bak
seven_control.v
seven_control.v.bak
transcript
vsim.wlf
work
....\counter
....\.......\verilog.asm
....\.......\_primary.dat
....\.......\_primary.vhd
....\counter_0to9999
....\...............\verilog.asm
....\...............\_primary.dat
....\...............\_primary.vhd
....\counter_divider
....\...............\verilog.asm
....\...............\_primary.dat
....\...............\_primary.vhd
....\counter_tb
....\..........\verilog.asm
....\..........\_primary.dat
....\..........\_primary.vhd
....\sevenseg_display
....\................\verilog.asm
....\................\_primary.dat
....\................\_primary.vhd
....\seven_contrl
....\............\verilog.asm
....\............\_primary.dat
....\............\_primary.vhd
....\_info