文件名称:xapp860
介绍说明－－下载内容均来自于网络，请自行研究使用
16通道DDR的LVDS接口（VHDL,Verilog and doc）-16-Channel, DDR LVDS Interface with
Real-Time Window Monitoring
Real-Time Window Monitoring
(系统自动生成,下载前可以参看下载内容)
下载文件列表
readme.txt
VERILOG
.......\BIT_ALIGN_MACHINE.v
.......\DDR_6TO1_16CHAN_RT_RX.v
.......\DDR_6TO1_16CHAN_RT_TX.v
.......\RESOURCE_SHARING_CONTROL.v
.......\RT_WINDOW_MONITOR.v
VHDL
....\BIT_ALIGN_MACHINE.vhd
....\count_to_128.vhd
....\count_to_16x.vhd
....\COUNT_TO_64.vhd
....\DDR_6TO1_16CHAN_RT_RX.vhd
....\DDR_6TO1_16CHAN_RT_TX.vhd
....\RESOURCE_SHARING_CONTROL.vhd
....\RT_WINDOW_MONITOR.vhd
....\seven_bit_reg_w_ce.vhd
xapp860.pdf
VERILOG
.......\BIT_ALIGN_MACHINE.v
.......\DDR_6TO1_16CHAN_RT_RX.v
.......\DDR_6TO1_16CHAN_RT_TX.v
.......\RESOURCE_SHARING_CONTROL.v
.......\RT_WINDOW_MONITOR.v
VHDL
....\BIT_ALIGN_MACHINE.vhd
....\count_to_128.vhd
....\count_to_16x.vhd
....\COUNT_TO_64.vhd
....\DDR_6TO1_16CHAN_RT_RX.vhd
....\DDR_6TO1_16CHAN_RT_TX.vhd
....\RESOURCE_SHARING_CONTROL.vhd
....\RT_WINDOW_MONITOR.vhd
....\seven_bit_reg_w_ce.vhd
xapp860.pdf