文件名称:DE2_NET
介绍说明－－下载内容均来自于网络，请自行研究使用
用DE2开发板实现的网络控制器。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。程序已经过测试，功能完好。-DE2 development board with the realization of the network controller. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in Nios2. Procedure has been tested, function well.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DE2_NET
.......\altpllpll_0.ppf
.......\Audio_0.v
.......\Audio_DAC_FIFO
.......\..............\cb_generator.pl
.......\..............\class.ptf
.......\..............\hdl
.......\..............\...\AUDIO_DAC_FIFO.v
.......\..............\...\FIFO_16_256.v
.......\AUDIO_DAC_FIFO.v
.......\Audio_PLL.ppf
.......\Audio_PLL.v
.......\bht_ram.mif
.......\Binary_VGA_Controller
.......\.....................\cb_generator.pl
.......\.....................\class.ptf
.......\.....................\hdl
.......\.....................\...\Img_DATA.hex
.......\.....................\...\Img_RAM.v
.......\.....................\...\VGA_Controller.v
.......\.....................\...\VGA_NIOS_CTRL.v
.......\.....................\...\VGA_OSD_RAM.v
.......\.....................\...\VGA_Param.h
.......\.....................\inc
.......\.....................\...\VGA.c
.......\.....................\...\VGA.h
.......\button_pio.v
.......\clock_0.v
.......\clock_1.v
.......\cpu_0.ocp
.......\cpu_0.v
.......\cpu_0.vo
.......\cpu_0_bht_ram.mif
.......\cpu_0_dc_tag_ram.mif
.......\cpu_0_ic_tag_ram.mif
.......\cpu_0_jtag_debug_module.v
.......\cpu_0_jtag_debug_module_wrapper.v
.......\cpu_0_mult_cell.v
.......\cpu_0_ociram_default_contents.mif
.......\cpu_0_rf_ram_a.mif
.......\cpu_0_rf_ram_b.mif
.......\cpu_0_test_bench.v
.......\dc_tag_ram.mif
.......\DE2_Board
.......\.........\class.ptf
.......\.........\system
.......\.........\......\asmi.v
.......\.........\......\cmp_state.ini
.......\.........\......\cpu_0.ocp
.......\.........\......\cpu_0.v
.......\.........\......\cpu_0_test_bench.v
.......\.........\......\data_RAM.hex
.......\.........\......\data_RAM.v
.......\.........\......\DE2_Board.asm.rpt
.......\.........\......\DE2_Board.bsf
.......\.........\......\DE2_Board.cdf
.......\.........\......\DE2_Board.done
.......\.........\......\DE2_Board.fit.eqn
.......\.........\......\DE2_Board.fit.rpt
.......\.........\......\DE2_Board.fit.summary
.......\.........\......\DE2_Board.flow.rpt
.......\.........\......\DE2_Board.map.eqn
.......\.........\......\DE2_Board.map.rpt
.......\.........\......\DE2_Board.map.summary
.......\.........\......\DE2_Board.pin
.......\.........\......\DE2_Board.pof
.......\.........\......\DE2_Board.ptf
.......\.........\......\DE2_Board.ptf.5.00
.......\.........\......\DE2_Board.ptf.bak
.......\.........\......\DE2_Board.qpf
.......\.........\......\DE2_Board.qsf
.......\.........\......\DE2_Board.qws
.......\.........\......\DE2_Board.sof
.......\.........\......\DE2_Board.tan.rpt
.......\.........\......\DE2_Board.tan.summary
.......\.........\......\DE2_Board.v
.......\.........\......\DE2_Board_assignment_defaults.qdf
.......\.........\......\DE2_Board_generation_script
.......\.........\......\DE2_Board_log.txt
.......\.........\......\DE2_Board_setup_quartus.tcl
.......\.........\......\DE2_Board_sim
.......\.........\......\.............\atail-f.pl
.......\.........\......\.............\contents_file_warning.txt
.......\.........\......\.............\jtag_uart_0_input_mutex.dat
.......\.........\......\.............\jtag_uart_0_input_stream.dat
.......\.........\......\.............\jtag_uart_0_output_stream.dat
.......\.........\......\DE2_Board_top.bdf
.......\.........\......\delay_reset_block.bdf
.......\.........\......\firmware_ROM.hex
.......\.........\......\firmware_ROM.v
.......\.........\......\jtag_uart_0.v
.......\.........\......\payload_buffer.hex
.......\.........\......\payload_buffer.v
.......\.........\......\reset_counter.v
.......\.........\......\rf_ram.mif
.......\.........\......\sopc_builder_debug_log.txt
.......\.........\......\sysid.v
.......\DE2_NET.dpf
.......\DE2_NET.pof
.......\DE2_NET.qpf
.......\altpllpll_0.ppf
.......\Audio_0.v
.......\Audio_DAC_FIFO
.......\..............\cb_generator.pl
.......\..............\class.ptf
.......\..............\hdl
.......\..............\...\AUDIO_DAC_FIFO.v
.......\..............\...\FIFO_16_256.v
.......\AUDIO_DAC_FIFO.v
.......\Audio_PLL.ppf
.......\Audio_PLL.v
.......\bht_ram.mif
.......\Binary_VGA_Controller
.......\.....................\cb_generator.pl
.......\.....................\class.ptf
.......\.....................\hdl
.......\.....................\...\Img_DATA.hex
.......\.....................\...\Img_RAM.v
.......\.....................\...\VGA_Controller.v
.......\.....................\...\VGA_NIOS_CTRL.v
.......\.....................\...\VGA_OSD_RAM.v
.......\.....................\...\VGA_Param.h
.......\.....................\inc
.......\.....................\...\VGA.c
.......\.....................\...\VGA.h
.......\button_pio.v
.......\clock_0.v
.......\clock_1.v
.......\cpu_0.ocp
.......\cpu_0.v
.......\cpu_0.vo
.......\cpu_0_bht_ram.mif
.......\cpu_0_dc_tag_ram.mif
.......\cpu_0_ic_tag_ram.mif
.......\cpu_0_jtag_debug_module.v
.......\cpu_0_jtag_debug_module_wrapper.v
.......\cpu_0_mult_cell.v
.......\cpu_0_ociram_default_contents.mif
.......\cpu_0_rf_ram_a.mif
.......\cpu_0_rf_ram_b.mif
.......\cpu_0_test_bench.v
.......\dc_tag_ram.mif
.......\DE2_Board
.......\.........\class.ptf
.......\.........\system
.......\.........\......\asmi.v
.......\.........\......\cmp_state.ini
.......\.........\......\cpu_0.ocp
.......\.........\......\cpu_0.v
.......\.........\......\cpu_0_test_bench.v
.......\.........\......\data_RAM.hex
.......\.........\......\data_RAM.v
.......\.........\......\DE2_Board.asm.rpt
.......\.........\......\DE2_Board.bsf
.......\.........\......\DE2_Board.cdf
.......\.........\......\DE2_Board.done
.......\.........\......\DE2_Board.fit.eqn
.......\.........\......\DE2_Board.fit.rpt
.......\.........\......\DE2_Board.fit.summary
.......\.........\......\DE2_Board.flow.rpt
.......\.........\......\DE2_Board.map.eqn
.......\.........\......\DE2_Board.map.rpt
.......\.........\......\DE2_Board.map.summary
.......\.........\......\DE2_Board.pin
.......\.........\......\DE2_Board.pof
.......\.........\......\DE2_Board.ptf
.......\.........\......\DE2_Board.ptf.5.00
.......\.........\......\DE2_Board.ptf.bak
.......\.........\......\DE2_Board.qpf
.......\.........\......\DE2_Board.qsf
.......\.........\......\DE2_Board.qws
.......\.........\......\DE2_Board.sof
.......\.........\......\DE2_Board.tan.rpt
.......\.........\......\DE2_Board.tan.summary
.......\.........\......\DE2_Board.v
.......\.........\......\DE2_Board_assignment_defaults.qdf
.......\.........\......\DE2_Board_generation_script
.......\.........\......\DE2_Board_log.txt
.......\.........\......\DE2_Board_setup_quartus.tcl
.......\.........\......\DE2_Board_sim
.......\.........\......\.............\atail-f.pl
.......\.........\......\.............\contents_file_warning.txt
.......\.........\......\.............\jtag_uart_0_input_mutex.dat
.......\.........\......\.............\jtag_uart_0_input_stream.dat
.......\.........\......\.............\jtag_uart_0_output_stream.dat
.......\.........\......\DE2_Board_top.bdf
.......\.........\......\delay_reset_block.bdf
.......\.........\......\firmware_ROM.hex
.......\.........\......\firmware_ROM.v
.......\.........\......\jtag_uart_0.v
.......\.........\......\payload_buffer.hex
.......\.........\......\payload_buffer.v
.......\.........\......\reset_counter.v
.......\.........\......\rf_ram.mif
.......\.........\......\sopc_builder_debug_log.txt
.......\.........\......\sysid.v
.......\DE2_NET.dpf
.......\DE2_NET.pof
.......\DE2_NET.qpf