文件名称:RD1011_rev01.2
介绍说明－－下载内容均来自于网络，请自行研究使用
采用VHDL实现的UART硬件模块，该模块包括了modem的硬件实现，已经仿真测试代码，顶层模块可以采用VHDL或verilog实现，便于嵌入到自己的设计之中。文档中附有详细的使用说明和注释。-Achieved using VHDL hardware UART module, the module includes the hardware modem has simulation test code modules can be used top-level VHDL or verilog to achieve easy embedded into the design of their own. Document with detailed instructions and notes.
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下载文件列表
RD1011
......\docs
......\....\RD1011.pdf
......\....\rd1011_readme.txt
......\project
......\.......\4KZE
......\.......\....\UART_4K.lci
......\.......\....\UART_4K.syn
......\.......\....\uart_int_tb_vhda.udo
......\.......\....\uart_int_tb_vhdaf.udo
......\.......\....\uart_rx_tb_vhda.udo
......\.......\....\uart_rx_tb_vhdaf.udo
......\.......\....\uart_tx_tb_vhda.udo
......\.......\....\uart_tx_tb_vhdaf.udo
......\.......\XO
......\.......\..\uart.lpf
......\.......\..\UART.syn
......\.......\..\uart_int_tb_vhdf.udo
......\.......\..\uart_int_tb_vhdr.udo
......\.......\..\uart_rx_tb_vhdf.udo
......\.......\..\uart_rx_tb_vhdr.udo
......\.......\..\uart_tx_tb_vhdf.udo
......\.......\..\uart_tx_tb_vhdr.udo
......\source
......\......\intface.vhd
......\......\modem.vhd
......\......\rxcver.vhd
......\......\txmitt.vhd
......\......\uart_top.vhd
......\......\UART_VerilogWrapper_TOP.v
......\testbench
......\.........\uart_int_tb.vhd
......\.........\uart_rx_tb.vhd
......\.........\uart_tx_tb.vhd
......\docs
......\....\RD1011.pdf
......\....\rd1011_readme.txt
......\project
......\.......\4KZE
......\.......\....\UART_4K.lci
......\.......\....\UART_4K.syn
......\.......\....\uart_int_tb_vhda.udo
......\.......\....\uart_int_tb_vhdaf.udo
......\.......\....\uart_rx_tb_vhda.udo
......\.......\....\uart_rx_tb_vhdaf.udo
......\.......\....\uart_tx_tb_vhda.udo
......\.......\....\uart_tx_tb_vhdaf.udo
......\.......\XO
......\.......\..\uart.lpf
......\.......\..\UART.syn
......\.......\..\uart_int_tb_vhdf.udo
......\.......\..\uart_int_tb_vhdr.udo
......\.......\..\uart_rx_tb_vhdf.udo
......\.......\..\uart_rx_tb_vhdr.udo
......\.......\..\uart_tx_tb_vhdf.udo
......\.......\..\uart_tx_tb_vhdr.udo
......\source
......\......\intface.vhd
......\......\modem.vhd
......\......\rxcver.vhd
......\......\txmitt.vhd
......\......\uart_top.vhd
......\......\UART_VerilogWrapper_TOP.v
......\testbench
......\.........\uart_int_tb.vhd
......\.........\uart_rx_tb.vhd
......\.........\uart_tx_tb.vhd