文件名称:74HC161
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74ls161 基于verilog语言的实现 源程序在压缩包的hdl文件夹中-74ls161 language based on the realization of verilog source package in compressed folder hdl
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下载文件列表
74hc161
.......\74hc161.prj
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\count4.adb
.......\........\.....\count4.dtf
.......\........\.....\..........\verify.log
.......\........\.....\count4.ide_des
.......\........\.....\count4.pdb
.......\........\.....\count4.pdb.depends
.......\........\.....\count4.tcl
.......\........\.....\count4_ba.sdf
.......\........\.....\count4_ba.v
.......\........\.....\count4_fp
.......\........\.....\.........\$$FlashPro_07294.L$$
.......\........\.....\.........\count4.log
.......\........\.....\.........\count4.pro
.......\........\.....\.........\projectData
.......\........\.....\.........\...........\count4.pdb
.......\........\.....\designer.log
.......\........\.....\designer_gen_ba.log
.......\........\.....\simulation
.......\........\.....\testbench.ide_des
.......\hdl
.......\...\74hc161.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\count4
.......\..........\........\......\verilog.psm
.......\..........\........\......\_primary.dat
.......\..........\........\......\_primary.dbs
.......\..........\........\......\_primary.vhd
.......\..........\........\testbench
.......\..........\........\.........\verilog.psm
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\_vmake
.......\..........\run.do
.......\..........\vsim.wlf
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\........\BtimErrors.log
.......\........\count4.dsk
.......\........\count4.hpj
.......\........\files_to_build.txt
.......\........\testbench.v
.......\........\waveperl.log
.......\synthesis
.......\.........\.recordref
.......\.........\AutoConstraint_count4.sdc
.......\.........\backup
.......\.........\......\count4.srr
.......\.........\coreip
.......\.........\count4.areasrr
.......\.........\count4.edn
.......\.........\count4.fse
.......\.........\count4.htm
.......\.........\count4.map
.......\.........\count4.pdc
.......\.........\count4.sap
.......\.........\count4.sdf
.......\.........\count4.so
.......\.........\count4.srd
.......\.........\count4.srm
.......\.........\count4.srr
.......\.........\count4.srs
.......\.........\count4.szr
.......\.........\count4.tlg
.......\.........\count4_sdc.sdc
.......\.........\count4_syn.prd
.......\.........\count4_syn.prj
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\count4.plg
.......\.........\......\count4_flink.htm
.......\.........\......\count4_srr.htm
.......\.........\......\count4_toc.htm
.......\.........\......\sap.log
.......\.........\traplog.tlg
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
74hc161.pdf
.......\74hc161.prj
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\count4.adb
.......\........\.....\count4.dtf
.......\........\.....\..........\verify.log
.......\........\.....\count4.ide_des
.......\........\.....\count4.pdb
.......\........\.....\count4.pdb.depends
.......\........\.....\count4.tcl
.......\........\.....\count4_ba.sdf
.......\........\.....\count4_ba.v
.......\........\.....\count4_fp
.......\........\.....\.........\$$FlashPro_07294.L$$
.......\........\.....\.........\count4.log
.......\........\.....\.........\count4.pro
.......\........\.....\.........\projectData
.......\........\.....\.........\...........\count4.pdb
.......\........\.....\designer.log
.......\........\.....\designer_gen_ba.log
.......\........\.....\simulation
.......\........\.....\testbench.ide_des
.......\hdl
.......\...\74hc161.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\count4
.......\..........\........\......\verilog.psm
.......\..........\........\......\_primary.dat
.......\..........\........\......\_primary.dbs
.......\..........\........\......\_primary.vhd
.......\..........\........\testbench
.......\..........\........\.........\verilog.psm
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\_vmake
.......\..........\run.do
.......\..........\vsim.wlf
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\........\BtimErrors.log
.......\........\count4.dsk
.......\........\count4.hpj
.......\........\files_to_build.txt
.......\........\testbench.v
.......\........\waveperl.log
.......\synthesis
.......\.........\.recordref
.......\.........\AutoConstraint_count4.sdc
.......\.........\backup
.......\.........\......\count4.srr
.......\.........\coreip
.......\.........\count4.areasrr
.......\.........\count4.edn
.......\.........\count4.fse
.......\.........\count4.htm
.......\.........\count4.map
.......\.........\count4.pdc
.......\.........\count4.sap
.......\.........\count4.sdf
.......\.........\count4.so
.......\.........\count4.srd
.......\.........\count4.srm
.......\.........\count4.srr
.......\.........\count4.srs
.......\.........\count4.szr
.......\.........\count4.tlg
.......\.........\count4_sdc.sdc
.......\.........\count4_syn.prd
.......\.........\count4_syn.prj
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\count4.plg
.......\.........\......\count4_flink.htm
.......\.........\......\count4_srr.htm
.......\.........\......\count4_toc.htm
.......\.........\......\sap.log
.......\.........\traplog.tlg
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
74hc161.pdf