文件名称:74HC373
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74hc373 基于verilog语言的实现 -Verilog language 74hc373 based on the realization of
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下载文件列表
74hc373
.......\74hc373.prj
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\designer.log
.......\........\.....\latch8.adb
.......\........\.....\latch8.dtf
.......\........\.....\..........\verify.log
.......\........\.....\latch8.ide_des
.......\........\.....\latch8.pdb
.......\........\.....\latch8.pdb.depends
.......\........\.....\latch8.tcl
.......\........\.....\latch8_fp
.......\........\.....\.........\$$FlashPro_07294.L$$
.......\........\.....\.........\latch8.log
.......\........\.....\.........\latch8.pro
.......\........\.....\.........\projectData
.......\........\.....\.........\...........\latch8.pdb
.......\........\.....\simulation
.......\hdl
.......\...\74hc373.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\latch8
.......\..........\........\......\verilog.psm
.......\..........\........\......\_primary.dat
.......\..........\........\......\_primary.dbs
.......\..........\........\......\_primary.vhd
.......\..........\........\testbench
.......\..........\........\.........\verilog.psm
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\_vmake
.......\..........\run.do
.......\..........\vsim.wlf
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\........\testbench.v
.......\synthesis
.......\.........\backup
.......\.........\......\latch8.srr
.......\.........\coreip
.......\.........\latch8.areasrr
.......\.........\latch8.edn
.......\.........\latch8.fse
.......\.........\latch8.htm
.......\.........\latch8.map
.......\.........\latch8.pdc
.......\.........\latch8.sap
.......\.........\latch8.sdf
.......\.........\latch8.so
.......\.........\latch8.srd
.......\.........\latch8.srm
.......\.........\latch8.srr
.......\.........\latch8.srs
.......\.........\latch8.szr
.......\.........\latch8.tlg
.......\.........\latch8_sdc.sdc
.......\.........\latch8_syn.prd
.......\.........\latch8_syn.prj
.......\.........\latch8_syn.sdc
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\latch8.plg
.......\.........\......\latch8_flink.htm
.......\.........\......\latch8_srr.htm
.......\.........\......\latch8_toc.htm
.......\.........\......\sap.log
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
74hc373.pdf
.......\74hc373.prj
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\designer.log
.......\........\.....\latch8.adb
.......\........\.....\latch8.dtf
.......\........\.....\..........\verify.log
.......\........\.....\latch8.ide_des
.......\........\.....\latch8.pdb
.......\........\.....\latch8.pdb.depends
.......\........\.....\latch8.tcl
.......\........\.....\latch8_fp
.......\........\.....\.........\$$FlashPro_07294.L$$
.......\........\.....\.........\latch8.log
.......\........\.....\.........\latch8.pro
.......\........\.....\.........\projectData
.......\........\.....\.........\...........\latch8.pdb
.......\........\.....\simulation
.......\hdl
.......\...\74hc373.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\latch8
.......\..........\........\......\verilog.psm
.......\..........\........\......\_primary.dat
.......\..........\........\......\_primary.dbs
.......\..........\........\......\_primary.vhd
.......\..........\........\testbench
.......\..........\........\.........\verilog.psm
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\_vmake
.......\..........\run.do
.......\..........\vsim.wlf
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\........\testbench.v
.......\synthesis
.......\.........\backup
.......\.........\......\latch8.srr
.......\.........\coreip
.......\.........\latch8.areasrr
.......\.........\latch8.edn
.......\.........\latch8.fse
.......\.........\latch8.htm
.......\.........\latch8.map
.......\.........\latch8.pdc
.......\.........\latch8.sap
.......\.........\latch8.sdf
.......\.........\latch8.so
.......\.........\latch8.srd
.......\.........\latch8.srm
.......\.........\latch8.srr
.......\.........\latch8.srs
.......\.........\latch8.szr
.......\.........\latch8.tlg
.......\.........\latch8_sdc.sdc
.......\.........\latch8_syn.prd
.......\.........\latch8_syn.prj
.......\.........\latch8_syn.sdc
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\latch8.plg
.......\.........\......\latch8_flink.htm
.......\.........\......\latch8_srr.htm
.......\.........\......\latch8_toc.htm
.......\.........\......\sap.log
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
74hc373.pdf