文件名称:DE2_70_TV
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--- --- --- -Verilog--- --- ----
This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.--------------------Verilog----------------
This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.--------------------Verilog----------------
This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
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下载文件列表
DE2_70_TV
.........\AUDIO_DAC.v
.........\db
.........\..\DE2_70_TV.db_info
.........\..\DE2_70_TV.eco.cdb
.........\..\DE2_70_TV.sld_design_entry.sci
.........\DE2_70_TV.pof
.........\DE2_70_TV.qpf
.........\DE2_70_TV.qsf
.........\DE2_70_TV.qws
.........\DE2_70_TV.sof
.........\DE2_70_TV.v
.........\DE2_70_TV_assignment_defaults.qdf
.........\DIV.v
.........\I2C_AV_Config.v
.........\I2C_Controller.v
.........\ITU_656_Decoder.v
.........\Line_Buffer.v
.........\MAC_3.v
.........\PLL.v
.........\README.txt
.........\Reset_Delay.v
.........\Sdram_Control_4Port
.........\...................\command.v
.........\...................\control_interface.v
.........\...................\Sdram_Control_4Port.v
.........\...................\Sdram_Params.h
.........\...................\Sdram_PLL.bsf
.........\...................\Sdram_PLL.ppf
.........\...................\Sdram_PLL.v
.........\...................\Sdram_RD_FIFO.v
.........\...................\Sdram_WR_FIFO.v
.........\...................\sdr_data_path.v
.........\SEG7_LUT.v
.........\SEG7_LUT_8.v
.........\TD_Detect.v
.........\TP_RAM.v
.........\VGA_Ctrl.v
.........\YCbCr2RGB.v
.........\YUV422_to_444.v
.........\AUDIO_DAC.v
.........\db
.........\..\DE2_70_TV.db_info
.........\..\DE2_70_TV.eco.cdb
.........\..\DE2_70_TV.sld_design_entry.sci
.........\DE2_70_TV.pof
.........\DE2_70_TV.qpf
.........\DE2_70_TV.qsf
.........\DE2_70_TV.qws
.........\DE2_70_TV.sof
.........\DE2_70_TV.v
.........\DE2_70_TV_assignment_defaults.qdf
.........\DIV.v
.........\I2C_AV_Config.v
.........\I2C_Controller.v
.........\ITU_656_Decoder.v
.........\Line_Buffer.v
.........\MAC_3.v
.........\PLL.v
.........\README.txt
.........\Reset_Delay.v
.........\Sdram_Control_4Port
.........\...................\command.v
.........\...................\control_interface.v
.........\...................\Sdram_Control_4Port.v
.........\...................\Sdram_Params.h
.........\...................\Sdram_PLL.bsf
.........\...................\Sdram_PLL.ppf
.........\...................\Sdram_PLL.v
.........\...................\Sdram_RD_FIFO.v
.........\...................\Sdram_WR_FIFO.v
.........\...................\sdr_data_path.v
.........\SEG7_LUT.v
.........\SEG7_LUT_8.v
.........\TD_Detect.v
.........\TP_RAM.v
.........\VGA_Ctrl.v
.........\YCbCr2RGB.v
.........\YUV422_to_444.v