文件名称:sim
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通用的循环码编码器和（7,4）循环码译码器。采用VERILOG HDL编写，通过硬件验证。需使用modelsim 5.6仿真-Common cyclic code encoder and (7,4) cyclic code decoder. VERILOG HDL preparation used by the hardware verification. Need to use simulation modelsim 5.6
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下载文件列表
sim
...\bm
...\..\bm.v
...\..\t_bm.v
...\..\vsim.wlf
...\..\work
...\..\....\bm
...\..\....\..\verilog.asm
...\..\....\..\_primary.dat
...\..\....\..\_primary.vhd
...\..\....\t_bm
...\..\....\....\verilog.asm
...\..\....\....\_primary.dat
...\..\....\....\_primary.vhd
...\..\....\_info
...\..\work.cr.mti
...\..\work.mpf
...\ym
...\..\alpha.cr.mti
...\..\alpha.mpf
...\..\transcript
...\..\vsim.wlf
...\..\work
...\..\....\ym
...\..\....\..\verilog.asm
...\..\....\..\_primary.dat
...\..\....\..\_primary.vhd
...\..\....\ym_t
...\..\....\....\verilog.asm
...\..\....\....\_primary.dat
...\..\....\....\_primary.vhd
...\..\....\_info
...\..\work.cr.mti
...\..\work.mpf
...\..\ym.v
...\..\ym_t.v
...\bm
...\..\bm.v
...\..\t_bm.v
...\..\vsim.wlf
...\..\work
...\..\....\bm
...\..\....\..\verilog.asm
...\..\....\..\_primary.dat
...\..\....\..\_primary.vhd
...\..\....\t_bm
...\..\....\....\verilog.asm
...\..\....\....\_primary.dat
...\..\....\....\_primary.vhd
...\..\....\_info
...\..\work.cr.mti
...\..\work.mpf
...\ym
...\..\alpha.cr.mti
...\..\alpha.mpf
...\..\transcript
...\..\vsim.wlf
...\..\work
...\..\....\ym
...\..\....\..\verilog.asm
...\..\....\..\_primary.dat
...\..\....\..\_primary.vhd
...\..\....\ym_t
...\..\....\....\verilog.asm
...\..\....\....\_primary.dat
...\..\....\....\_primary.vhd
...\..\....\_info
...\..\work.cr.mti
...\..\work.mpf
...\..\ym.v
...\..\ym_t.v