文件名称:uart
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用FPGA实现uart的verilog源码，包含standard framing error, parity control and overrun detection.-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
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下载文件列表
uart
....\rcvr.v
....\txmit.v
....\uart.v
....\rcvr.v
....\txmit.v
....\uart.v