文件名称:FPGA_work
介绍说明－－下载内容均来自于网络，请自行研究使用
实际上使用VerilogHDL语言写的，开发环境为Quartus7.2，很不错的，基于de2的-VerilogHDL the language actually used to write, and development environment for Quartus7.2, very good, based on the de2
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FPGA_work
.........\CLK_1Hz
.........\.......\CLK_1Hz.asm.rpt
.........\.......\CLK_1Hz.done
.........\.......\CLK_1Hz.fit.rpt
.........\.......\CLK_1Hz.fit.smsg
.........\.......\CLK_1Hz.fit.summary
.........\.......\CLK_1Hz.flow.rpt
.........\.......\CLK_1Hz.map.rpt
.........\.......\CLK_1Hz.map.summary
.........\.......\CLK_1Hz.pin
.........\.......\CLK_1Hz.pof
.........\.......\CLK_1Hz.qpf
.........\.......\CLK_1Hz.qsf
.........\.......\CLK_1Hz.qws
.........\.......\CLK_1Hz.sim.rpt
.........\.......\CLK_1Hz.sof
.........\.......\CLK_1Hz.tan.rpt
.........\.......\CLK_1Hz.tan.summary
.........\.......\CLK_1Hz.v
.........\.......\CLK_1Hz.v.bak
.........\.......\CLK_1Hz.vwf
.........\.......\db
.........\.......\..\CLK_1Hz.asm.qmsg
.........\.......\..\CLK_1Hz.asm_labs.ddb
.........\.......\..\CLK_1Hz.cbx.xml
.........\.......\..\CLK_1Hz.cmp.bpm
.........\.......\..\CLK_1Hz.cmp.cdb
.........\.......\..\CLK_1Hz.cmp.ecobp
.........\.......\..\CLK_1Hz.cmp.hdb
.........\.......\..\CLK_1Hz.cmp.logdb
.........\.......\..\CLK_1Hz.cmp.rdb
.........\.......\..\CLK_1Hz.cmp.tdb
.........\.......\..\CLK_1Hz.cmp0.ddb
.........\.......\..\CLK_1Hz.cmp_bb.cdb
.........\.......\..\CLK_1Hz.cmp_bb.hdb
.........\.......\..\CLK_1Hz.cmp_bb.logdb
.........\.......\..\CLK_1Hz.cmp_bb.rcf
.........\.......\..\CLK_1Hz.dbp
.........\.......\..\CLK_1Hz.db_info
.........\.......\..\CLK_1Hz.eco.cdb
.........\.......\..\CLK_1Hz.eds_overflow
.........\.......\..\CLK_1Hz.fit.qmsg
.........\.......\..\CLK_1Hz.fnsim.cdb
.........\.......\..\CLK_1Hz.fnsim.hdb
.........\.......\..\CLK_1Hz.fnsim.qmsg
.........\.......\..\CLK_1Hz.hier_info
.........\.......\..\CLK_1Hz.hif
.........\.......\..\CLK_1Hz.map.bpm
.........\.......\..\CLK_1Hz.map.cdb
.........\.......\..\CLK_1Hz.map.ecobp
.........\.......\..\CLK_1Hz.map.hdb
.........\.......\..\CLK_1Hz.map.logdb
.........\.......\..\CLK_1Hz.map.qmsg
.........\.......\..\CLK_1Hz.map_bb.cdb
.........\.......\..\CLK_1Hz.map_bb.hdb
.........\.......\..\CLK_1Hz.map_bb.logdb
.........\.......\..\CLK_1Hz.pre_map.cdb
.........\.......\..\CLK_1Hz.pre_map.hdb
.........\.......\..\CLK_1Hz.psp
.........\.......\..\CLK_1Hz.pss
.........\.......\..\CLK_1Hz.rpp.qmsg
.........\.......\..\CLK_1Hz.rtlv.hdb
.........\.......\..\CLK_1Hz.rtlv_sg.cdb
.........\.......\..\CLK_1Hz.rtlv_sg_swap.cdb
.........\.......\..\CLK_1Hz.sgate.rvd
.........\.......\..\CLK_1Hz.sgate_sm.rvd
.........\.......\..\CLK_1Hz.sgdiff.cdb
.........\.......\..\CLK_1Hz.sgdiff.hdb
.........\.......\..\CLK_1Hz.signalprobe.cdb
.........\.......\..\CLK_1Hz.sim.cvwf
.........\.......\..\CLK_1Hz.sim.hdb
.........\.......\..\CLK_1Hz.sim.qmsg
.........\.......\..\CLK_1Hz.sim.rdb
.........\.......\..\CLK_1Hz.simfam
.........\.......\..\CLK_1Hz.sld_design_entry.sci
.........\.......\..\CLK_1Hz.sld_design_entry_dsc.sci
.........\.......\..\CLK_1Hz.syn_hier_info
.........\.......\..\CLK_1Hz.tan.qmsg
.........\.......\..\CLK_1Hz.tis_db_list.ddb
.........\.......\..\prev_cmp_CLK_1Hz.asm.qmsg
.........\.......\..\prev_cmp_CLK_1Hz.fit.qmsg
.........\.......\..\prev_cmp_CLK_1Hz.map.qmsg
.........\.......\..\prev_cmp_CLK_1Hz.qmsg
.........\.......\..\prev_cmp_CLK_1Hz.sim.qmsg
.........\.......\..\prev_cmp_CLK_1Hz.tan.qmsg
.........\.......\..\wed.wsf
.........\FSM_1
.........\.....\db
.........\.....\..\FSM.asm.qmsg
.........\.....\..\FSM.asm_labs.ddb
.........\.....\..\FSM.cbx.xml
.........\.....\..\FSM.cmp.bpm
.........\.....\..\FSM.cmp.cdb
.........\.....\..\FSM.cmp.ecobp
.........\.....\..\FSM.cmp.hdb
.........\.....\..\FSM.cmp.logdb
.........\.....\..\FSM.cmp.rdb
.........\.....\..\FSM.cmp.tdb
.........\.....\..\FSM.cmp0.ddb
.........\CLK_1Hz
.........\.......\CLK_1Hz.asm.rpt
.........\.......\CLK_1Hz.done
.........\.......\CLK_1Hz.fit.rpt
.........\.......\CLK_1Hz.fit.smsg
.........\.......\CLK_1Hz.fit.summary
.........\.......\CLK_1Hz.flow.rpt
.........\.......\CLK_1Hz.map.rpt
.........\.......\CLK_1Hz.map.summary
.........\.......\CLK_1Hz.pin
.........\.......\CLK_1Hz.pof
.........\.......\CLK_1Hz.qpf
.........\.......\CLK_1Hz.qsf
.........\.......\CLK_1Hz.qws
.........\.......\CLK_1Hz.sim.rpt
.........\.......\CLK_1Hz.sof
.........\.......\CLK_1Hz.tan.rpt
.........\.......\CLK_1Hz.tan.summary
.........\.......\CLK_1Hz.v
.........\.......\CLK_1Hz.v.bak
.........\.......\CLK_1Hz.vwf
.........\.......\db
.........\.......\..\CLK_1Hz.asm.qmsg
.........\.......\..\CLK_1Hz.asm_labs.ddb
.........\.......\..\CLK_1Hz.cbx.xml
.........\.......\..\CLK_1Hz.cmp.bpm
.........\.......\..\CLK_1Hz.cmp.cdb
.........\.......\..\CLK_1Hz.cmp.ecobp
.........\.......\..\CLK_1Hz.cmp.hdb
.........\.......\..\CLK_1Hz.cmp.logdb
.........\.......\..\CLK_1Hz.cmp.rdb
.........\.......\..\CLK_1Hz.cmp.tdb
.........\.......\..\CLK_1Hz.cmp0.ddb
.........\.......\..\CLK_1Hz.cmp_bb.cdb
.........\.......\..\CLK_1Hz.cmp_bb.hdb
.........\.......\..\CLK_1Hz.cmp_bb.logdb
.........\.......\..\CLK_1Hz.cmp_bb.rcf
.........\.......\..\CLK_1Hz.dbp
.........\.......\..\CLK_1Hz.db_info
.........\.......\..\CLK_1Hz.eco.cdb
.........\.......\..\CLK_1Hz.eds_overflow
.........\.......\..\CLK_1Hz.fit.qmsg
.........\.......\..\CLK_1Hz.fnsim.cdb
.........\.......\..\CLK_1Hz.fnsim.hdb
.........\.......\..\CLK_1Hz.fnsim.qmsg
.........\.......\..\CLK_1Hz.hier_info
.........\.......\..\CLK_1Hz.hif
.........\.......\..\CLK_1Hz.map.bpm
.........\.......\..\CLK_1Hz.map.cdb
.........\.......\..\CLK_1Hz.map.ecobp
.........\.......\..\CLK_1Hz.map.hdb
.........\.......\..\CLK_1Hz.map.logdb
.........\.......\..\CLK_1Hz.map.qmsg
.........\.......\..\CLK_1Hz.map_bb.cdb
.........\.......\..\CLK_1Hz.map_bb.hdb
.........\.......\..\CLK_1Hz.map_bb.logdb
.........\.......\..\CLK_1Hz.pre_map.cdb
.........\.......\..\CLK_1Hz.pre_map.hdb
.........\.......\..\CLK_1Hz.psp
.........\.......\..\CLK_1Hz.pss
.........\.......\..\CLK_1Hz.rpp.qmsg
.........\.......\..\CLK_1Hz.rtlv.hdb
.........\.......\..\CLK_1Hz.rtlv_sg.cdb
.........\.......\..\CLK_1Hz.rtlv_sg_swap.cdb
.........\.......\..\CLK_1Hz.sgate.rvd
.........\.......\..\CLK_1Hz.sgate_sm.rvd
.........\.......\..\CLK_1Hz.sgdiff.cdb
.........\.......\..\CLK_1Hz.sgdiff.hdb
.........\.......\..\CLK_1Hz.signalprobe.cdb
.........\.......\..\CLK_1Hz.sim.cvwf
.........\.......\..\CLK_1Hz.sim.hdb
.........\.......\..\CLK_1Hz.sim.qmsg
.........\.......\..\CLK_1Hz.sim.rdb
.........\.......\..\CLK_1Hz.simfam
.........\.......\..\CLK_1Hz.sld_design_entry.sci
.........\.......\..\CLK_1Hz.sld_design_entry_dsc.sci
.........\.......\..\CLK_1Hz.syn_hier_info
.........\.......\..\CLK_1Hz.tan.qmsg
.........\.......\..\CLK_1Hz.tis_db_list.ddb
.........\.......\..\prev_cmp_CLK_1Hz.asm.qmsg
.........\.......\..\prev_cmp_CLK_1Hz.fit.qmsg
.........\.......\..\prev_cmp_CLK_1Hz.map.qmsg
.........\.......\..\prev_cmp_CLK_1Hz.qmsg
.........\.......\..\prev_cmp_CLK_1Hz.sim.qmsg
.........\.......\..\prev_cmp_CLK_1Hz.tan.qmsg
.........\.......\..\wed.wsf
.........\FSM_1
.........\.....\db
.........\.....\..\FSM.asm.qmsg
.........\.....\..\FSM.asm_labs.ddb
.........\.....\..\FSM.cbx.xml
.........\.....\..\FSM.cmp.bpm
.........\.....\..\FSM.cmp.cdb
.........\.....\..\FSM.cmp.ecobp
.........\.....\..\FSM.cmp.hdb
.........\.....\..\FSM.cmp.logdb
.........\.....\..\FSM.cmp.rdb
.........\.....\..\FSM.cmp.tdb
.........\.....\..\FSM.cmp0.ddb