文件名称:jpegVerilog
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FPGA实现jpeg Verilog源代码-FPGA realization of jpeg Verilog source code
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下载文件列表
jpegVerilog
...........\fpga-jpeg
...........\.........\dct
...........\.........\...\dct.v
...........\.........\...\dctu.v
...........\.........\...\dctub.v
...........\.........\...\dct_bench
...........\.........\...\.........\bench_top.v
...........\.........\...\dct_cos_table.v
...........\.........\...\dct_mac.v
...........\.........\...\dct_syn.v
...........\.........\...\fdct.v
...........\.........\...\huffman
...........\.........\...\.......\bench
...........\.........\...\.......\.....\bench_top.v
...........\.........\...\.......\.....\generic_dpram.v
...........\.........\...\.......\.....\generic_fifo_lfsr.v
...........\.........\...\.......\.....\lfsr.v
...........\.........\...\.......\.....\timescale.v
...........\.........\...\.......\huffman_dec.v
...........\.........\...\.......\huffman_enc.v
...........\.........\...\.......\huffman_tables.v
...........\.........\...\ro_cnt.v
...........\.........\...\rtl_sim
...........\.........\...\.......\Makefile.txt
...........\.........\...\ud_cnt.v
...........\.........\...\zigzag.v
...........\.........\jpeg
...........\.........\....\bench_top
...........\.........\....\.........\jpeg_encoder.v
...........\.........\....\jpeg_encoder.v
...........\.........\....\sim
...........\.........\....\...\cds.lib
...........\.........\....\...\hdl.var
...........\.........\....\...\Makefile.txt
...........\.........\qnr
...........\.........\...\attic
...........\.........\...\.....\div.v
...........\.........\...\.....\div_us.v
...........\.........\...\.....\ro_cnt.v
...........\.........\...\.....\ud_cnt.v
...........\.........\...\bench
...........\.........\...\.....\bench_div_top.v
...........\.........\...\.....\bench_qnr_top.v
...........\.........\...\.....\timescale.v
...........\.........\...\div_su.v
...........\.........\...\div_uu.v
...........\.........\...\jpeg_qnr.v
...........\.........\rgb2ycrcb
...........\.........\.........\modelsim.ini
...........\.........\.........\rgb2ycrcb
...........\.........\.........\.........\_info
...........\.........\.........\rgb2ycrcb.mpf
...........\.........\.........\rgb2ycrcb.v
...........\.........\.........\rgb2ycrcb_testbench.v
...........\.........\.........\rgb2ycrcb_webAddress.txt
...........\.........\.........\tcl_stacktrace.txt
...........\.........\.........\transcript
...........\.........\.........\work
...........\.........\.........\....\_info
...........\.........\run_length_coding
...........\.........\.................\attic
...........\.........\.................\.....\jpeg_rle2.v
...........\.........\.................\bench
...........\.........\.................\.....\bench.v.txt
...........\.........\.................\jpeg_rle.v
...........\.........\.................\jpeg_rle1.v
...........\.........\.................\jpeg_rzs.v
...........\fpga-jpeg
...........\.........\dct
...........\.........\...\dct.v
...........\.........\...\dctu.v
...........\.........\...\dctub.v
...........\.........\...\dct_bench
...........\.........\...\.........\bench_top.v
...........\.........\...\dct_cos_table.v
...........\.........\...\dct_mac.v
...........\.........\...\dct_syn.v
...........\.........\...\fdct.v
...........\.........\...\huffman
...........\.........\...\.......\bench
...........\.........\...\.......\.....\bench_top.v
...........\.........\...\.......\.....\generic_dpram.v
...........\.........\...\.......\.....\generic_fifo_lfsr.v
...........\.........\...\.......\.....\lfsr.v
...........\.........\...\.......\.....\timescale.v
...........\.........\...\.......\huffman_dec.v
...........\.........\...\.......\huffman_enc.v
...........\.........\...\.......\huffman_tables.v
...........\.........\...\ro_cnt.v
...........\.........\...\rtl_sim
...........\.........\...\.......\Makefile.txt
...........\.........\...\ud_cnt.v
...........\.........\...\zigzag.v
...........\.........\jpeg
...........\.........\....\bench_top
...........\.........\....\.........\jpeg_encoder.v
...........\.........\....\jpeg_encoder.v
...........\.........\....\sim
...........\.........\....\...\cds.lib
...........\.........\....\...\hdl.var
...........\.........\....\...\Makefile.txt
...........\.........\qnr
...........\.........\...\attic
...........\.........\...\.....\div.v
...........\.........\...\.....\div_us.v
...........\.........\...\.....\ro_cnt.v
...........\.........\...\.....\ud_cnt.v
...........\.........\...\bench
...........\.........\...\.....\bench_div_top.v
...........\.........\...\.....\bench_qnr_top.v
...........\.........\...\.....\timescale.v
...........\.........\...\div_su.v
...........\.........\...\div_uu.v
...........\.........\...\jpeg_qnr.v
...........\.........\rgb2ycrcb
...........\.........\.........\modelsim.ini
...........\.........\.........\rgb2ycrcb
...........\.........\.........\.........\_info
...........\.........\.........\rgb2ycrcb.mpf
...........\.........\.........\rgb2ycrcb.v
...........\.........\.........\rgb2ycrcb_testbench.v
...........\.........\.........\rgb2ycrcb_webAddress.txt
...........\.........\.........\tcl_stacktrace.txt
...........\.........\.........\transcript
...........\.........\.........\work
...........\.........\.........\....\_info
...........\.........\run_length_coding
...........\.........\.................\attic
...........\.........\.................\.....\jpeg_rle2.v
...........\.........\.................\bench
...........\.........\.................\.....\bench.v.txt
...........\.........\.................\jpeg_rle.v
...........\.........\.................\jpeg_rle1.v
...........\.........\.................\jpeg_rzs.v