文件名称:i2c
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下载文件列表
i2c
...\bench
...\.....\i2c_slave_model.v
...\.....\spi_slave_model.v
...\.....\tst_bench_top.v
...\.....\wb_master_model.v
...\doc
...\...\i2c_rev03.pdf
...\...\i2c_rev04.pdf
...\...\i2c_rev05.pdf
...\...\I2C_specs.doc
...\...\i2c_specs.pdf
...\infomation
...\..........\i2c_rev03.pdf
...\..........\I2C_specs.doc
...\rtl
...\...\i2c_master_bit_ctrl.v
...\...\i2c_master_byte_ctrl.v
...\...\i2c_master_defines.v
...\...\i2c_master_top.v
...\...\timescale.v
...\...\transcript
...\sim
...\...\bench.vcd
...\...\ncverilog.key
...\...\ncverilog.log
...\...\run.f
...\...\run.txt
...\y
...\.\oc_i2c_master.h
...\bench
...\.....\i2c_slave_model.v
...\.....\spi_slave_model.v
...\.....\tst_bench_top.v
...\.....\wb_master_model.v
...\doc
...\...\i2c_rev03.pdf
...\...\i2c_rev04.pdf
...\...\i2c_rev05.pdf
...\...\I2C_specs.doc
...\...\i2c_specs.pdf
...\infomation
...\..........\i2c_rev03.pdf
...\..........\I2C_specs.doc
...\rtl
...\...\i2c_master_bit_ctrl.v
...\...\i2c_master_byte_ctrl.v
...\...\i2c_master_defines.v
...\...\i2c_master_top.v
...\...\timescale.v
...\...\transcript
...\sim
...\...\bench.vcd
...\...\ncverilog.key
...\...\ncverilog.log
...\...\run.f
...\...\run.txt
...\y
...\.\oc_i2c_master.h