Final_project

.............\asyn_receiver.v

.............\control_wr_rd_for_SRAM.v

.............\copy_lena_3.hex

.............\db

.............\..\altsyncram_4qc1.tdf

.............\..\altsyncram_6sj1.tdf

.............\..\a_dpfifo_8ku.tdf

.............\..\a_fefifo_u7e.tdf

.............\..\cntr_el8.tdf

.............\..\cntr_sj7.tdf

.............\..\decode_4oa.tdf

.............\..\dpram_4it.tdf

.............\..\kit_DE2.asm.qmsg

.............\..\kit_DE2.asm_labs.ddb

.............\..\kit_DE2.cbx.xml

.............\..\kit_DE2.cmp.cdb

.............\..\kit_DE2.cmp.hdb

.............\..\kit_DE2.cmp.kpt

.............\..\kit_DE2.cmp.logdb

.............\..\kit_DE2.cmp.rdb

.............\..\kit_DE2.cmp.tdb

.............\..\kit_DE2.cmp0.ddb

.............\..\kit_DE2.dbp

.............\..\kit_DE2.db_info

.............\..\kit_DE2.eco.cdb

.............\..\kit_DE2.fit.qmsg

.............\..\kit_DE2.hier_info

.............\..\kit_DE2.hif

.............\..\kit_DE2.map.cdb

.............\..\kit_DE2.map.hdb

.............\..\kit_DE2.map.logdb

.............\..\kit_DE2.map.qmsg

.............\..\kit_DE2.pre_map.cdb

.............\..\kit_DE2.pre_map.hdb

.............\..\kit_DE2.psp

.............\..\kit_DE2.rpp.qmsg

.............\..\kit_DE2.rtlv.hdb

.............\..\kit_DE2.rtlv_sg.cdb

.............\..\kit_DE2.rtlv_sg_swap.cdb

.............\..\kit_DE2.sgate.rvd

.............\..\kit_DE2.sgate_sm.rvd

.............\..\kit_DE2.sgdiff.cdb

.............\..\kit_DE2.sgdiff.hdb

.............\..\kit_DE2.signalprobe.cdb

.............\..\kit_DE2.sld_design_entry.sci

.............\..\kit_DE2.sld_design_entry_dsc.sci

.............\..\kit_DE2.smp_dump.txt

.............\..\kit_DE2.syn_hier_info

.............\..\kit_DE2.tan.qmsg

.............\..\mux_kib.tdf

.............\..\scfifo_1eu.tdf

.............\FIFO_Image.v



.............\FIFO_Image_waveforms.html

.............\Khoi_FIFO.v

.............\kit_DE2.asm.rpt

.............\kit_DE2.cdf

.............\kit_DE2.done

.............\kit_DE2.fit.rpt

.............\kit_DE2.fit.summary

.............\kit_DE2.flow.rpt

.............\kit_DE2.map.rpt

.............\kit_DE2.map.summary

.............\kit_DE2.pin

.............\kit_DE2.pof

.............\kit_DE2.qpf

.............\kit_DE2.qsf

.............\kit_DE2.qws

.............\kit_DE2.sof

.............\kit_DE2.tan.rpt

.............\kit_DE2.tan.summary

.............\kit_DE2.v

.............\New Folder

.............\..........\asyn_receiver.v

.............\..........\control_wr_rd_for_SRAM.v

.............\..........\FIFO_Image.v

.............\..........\Khoi_FIFO.v

.............\..........\kit_DE2.v

.............\..........\Processing_image.v

.............\..........\Processing_image_0.v

.............\..........\Processing_image_1.v

.............\..........\ram_vga.v

.............\..........\SRAM_interface.v

.............\..........\vga_controller.v

.............\..........\vga_sync.v

.............\Processing_image.v

.............\Processing_image_0.v

.............\Processing_image_1.v

.............\ram_vga.v

.............\SRAM_interface.v

.............\vga_controller.v

.............\vga_sync.v