文件名称:clk4
介绍说明－－下载内容均来自于网络，请自行研究使用
clk4 时钟分频设计用于FPGA入门设计-clk4 clock divider is designed for FPGA design entry
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clk4
....\clk4.flow.rpt
....\clk4.map.rpt
....\clk4.map.summary
....\clk4.qpf
....\clk4.qsf
....\clk4.qws
....\clk4.v
....\clk4.v.bak
....\clk4_description.txt
....\db
....\..\clk4.cbx.xml
....\..\clk4.cmp.rdb
....\..\clk4.db_info
....\..\clk4.eco.cdb
....\..\clk4.hif
....\..\clk4.map.qmsg
....\..\clk4.sld_design_entry.sci
....\..\clk4.sld_design_entry_dsc.sci
....\..\prev_cmp_clk4.map.qmsg
....\prev_cmp_clk4.qmsg
....\clk4.flow.rpt
....\clk4.map.rpt
....\clk4.map.summary
....\clk4.qpf
....\clk4.qsf
....\clk4.qws
....\clk4.v
....\clk4.v.bak
....\clk4_description.txt
....\db
....\..\clk4.cbx.xml
....\..\clk4.cmp.rdb
....\..\clk4.db_info
....\..\clk4.eco.cdb
....\..\clk4.hif
....\..\clk4.map.qmsg
....\..\clk4.sld_design_entry.sci
....\..\clk4.sld_design_entry_dsc.sci
....\..\prev_cmp_clk4.map.qmsg
....\prev_cmp_clk4.qmsg